Supporting 8-bit floating point format operands in a computing architecture

ABSTRACT

An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

FIELD

This document relates generally to data processing and more particularly to supporting 8-bit floating point format operands in a computing architecture.

BACKGROUND

Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

To further increase performance, graphics processors typically implement processing techniques such as pipelining that attempt to process, in parallel, as much graphics data as possible throughout the different parts of the graphics pipeline. Parallel graphics processors with single instruction, multiple data (SIMD) or single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMD architecture, computers with multiple processing elements attempt to perform the same operation on multiple data points simultaneously. In a SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency.

Graphics processors are often be utilized for applications in the fields of artificial intelligence (AI) and machine learning (ML). Advances in these fields have enabled ML models to take advantage of low-precision arithmetic for training neural network. Conventional training platforms support floating point 16 (FP16) and brain floating point 16 (bfloat16 or BF16) data formats in high-performance systolic array implementations. Recent advances have been made to support training of deep neural networks using lower precision data formats, such as an 8-bit data formats. However, conventional systems provide no hardware support for performing operations using 8-bit floating point format operands.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope.

FIG. 1 is a block diagram of a processing system.

FIG. 2A-2D illustrate computing systems and graphics processors.

FIG. 3A-3C illustrate block diagrams of additional graphics processor and compute accelerator architectures.

FIG. 4 is a block diagram of a graphics processing engine of a graphics processor.

FIG. 5A-5B illustrate thread execution logic including an array of processing elements employed in a graphics processor core.

FIG. 6 illustrates an additional execution unit.

FIG. 7 is a block diagram illustrating a graphics processor instruction formats.

FIG. 8 is a block diagram of an additional graphics processor architecture.

FIG. 9A-9B illustrate a graphics processor command format and command sequence.

FIG. 10 illustrates example graphics software architecture for a data processing system.

FIG. 11A is a block diagram illustrating an IP core development system.

FIG. 11B illustrates a cross-section side view of an integrated circuit package assembly.

FIG. 11C illustrates a package assembly that includes multiple units of hardware logic chiplets connected to a substrate (e.g., base die).

FIG. 11D illustrates a package assembly including interchangeable chiplets.

FIG. 12 is a block diagram illustrating an example system on a chip integrated circuit.

FIG. 13A-13B are block diagrams illustrating example graphics processors for use within an SoC.

FIG. 14 is a block diagram of a data processing system, according to an embodiment.

FIG. 15 is a block diagram illustrating a brain-float 8 (BFLOAT8 or BF8) binary format, in accordance with embodiments.

FIG. 16 is a block diagram illustrating a systolic DP 8-bit FP format operation performed by an instruction pipeline, according to embodiments.

FIGS. 17A-17B are block diagrams illustrating a systolic array circuit to perform systolic dot product accumulate on 8-bit floating point format input operands, in accordance with embodiments.

FIG. 18A illustrates an instruction executable by a systolic array circuit, according to embodiments described herein.

FIG. 18B illustrates a program code compilation process, according to an embodiment.

FIG. 19 is a flow diagram illustrating an embodiment of a method for executing an instruction for systolic dot product accumulate on 8-bit floating point format input operands.

FIG. 20 is a flow diagram illustrating an embodiment of a method for systolic dot product accumulate on 8-bit floating point format input operands.

FIG. 21 is a block diagram illustrating an 8-bit FP format conversion operation performed by an instruction pipeline, according to embodiments.

FIG. 22A illustrates an instruction executable by a processing unit, according to embodiments described herein.

FIG. 22B illustrates a program code compilation process, according to an embodiment.

FIG. 23 is a flow diagram illustrating an embodiment of a method for executing an instruction for converting floating point data to 8-bit floating point format data.

FIG. 24 is a flow diagram illustrating an embodiment of a method for converting floating point data to 8-bit floating point format data.

FIG. 25 is a block diagram illustrating an 8-bit FP format conversion with stochastic rounding operation performed by an instruction pipeline, according to embodiments.

FIG. 26 is a block diagram illustrating fixed-point addition of sign-magnitude representation of the mantissa and the random number, in accordance with embodiments.

FIG. 27A illustrates an instruction executable by a processing unit, according to embodiments described herein.

FIG. 27B illustrates a program code compilation process, according to an embodiment.

FIG. 28 is a flow diagram illustrating an embodiment of a method for executing an instruction for performing efficient stochastic rounding on floating point values.

FIG. 29 is a flow diagram illustrating an embodiment of a method for performing efficient stochastic rounding on floating point values.

FIG. 30 is a block diagram illustrating two 8-bit floating point formats that use a different binary encoding and exponent bias, in accordance with embodiments.

FIG. 31 is a block diagram illustrating a hybrid 8-bit FP format systolic operation performed by an instruction pipeline, according to embodiments.

FIG. 32 is a block diagram illustrating a hybrid FMA unit of a systolic array circuit to perform hybrid floating point systolic operations, in accordance with embodiments.

FIG. 33A illustrates an instruction executable by a systolic array circuit, according to embodiments described herein.

FIG. 33B illustrates a program code compilation process, according to an embodiment.

FIG. 34 is a flow diagram illustrating an embodiment of a method for executing an instruction for hybrid floating point systolic operations.

FIG. 35 is a flow diagram illustrating an embodiment of a method for hybrid floating point systolic operations.

FIG. 36 is a block diagram illustrating a mixed mode 8-bit FP format operation performed by an instruction pipeline, according to embodiments.

FIG. 37 shows an example schematic representation of a hardware circuit to perform mixed mode MAC operation using at least one 8-bit FP format operand, in accordance with embodiments.

FIG. 38A illustrates a set of instructions executable by a processing unit, according to embodiments described herein.

FIG. 38B illustrates a program code compilation process, according to an embodiment.

FIG. 39 is a flow diagram illustrating an embodiment of a method for executing an instruction to perform mixed mode operations with 8-bit floating point format operands.

FIG. 40 is a flow diagram illustrating an embodiment of a method for performing mixed mode operations with 8-bit floating point format operands.

DETAILED DESCRIPTION

A graphics processing unit (GPU) is communicatively coupled to host/processor cores to accelerate, for example, graphics operations, machine-learning operations, pattern analysis operations, and/or various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor/cores over a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores over an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.

In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the present embodiments.

System Overview

FIG. 1 is a block diagram of a processing system 100, according to an embodiment. System 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, the system 100 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices such as within Internet-of-things (IoT) devices with wired or wireless connectivity to a local or wide area network.

In one embodiment, system 100 can include, couple with, or be integrated within: a server-based gaming platform; a game console, including a game and media console; a mobile gaming console, a handheld game console, or an online game console. In some embodiments the system 100 is part of a mobile phone, smart phone, tablet computing device or mobile Internet-connected device such as a laptop with low internal storage capacity. Processing system 100 can also include, couple with, or be integrated within: a wearable device, such as a smart watch wearable device; smart eyewear or clothing enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio or tactile outputs to supplement real world visual, audio or tactile experiences or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback; other augmented reality (AR) device; or other virtual reality (VR) device. In some embodiments, the processing system 100 includes or is part of a television or set top box device. In one embodiment, system 100 can include, couple with, or be integrated within a self-driving vehicle such as a bus, tractor trailer, car, motor or electric power cycle, plane or glider (or any combination thereof). The self-driving vehicle may use system 100 to process the environment sensed around the vehicle.

In some embodiments, the one or more processors 102 each include one or more processor cores 107 to process instructions which, when executed, perform operations for system or user software. In embodiments herein, a processor can refer to dedicated hardware circuitry for efficiently processing commands/instructions, and may be referred to as processor circuitry. In some embodiments, at least one of the one or more processor cores 107 is configured to process a specific instruction set 109. In some embodiments, instruction set 109 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). One or more processor cores 107 may process a different instruction set 109, which may include instructions to facilitate the emulation of other instruction sets. Processor core 107 may also include other processing devices, such as a Digital Signal Processor (DSP).

In some embodiments, the processor 102 includes cache memory 104. Depending on the architecture, the processor 102 can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 107 using known cache coherency techniques. A register file 106 can be additionally included in processor 102 and may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with one or more interface bus(es) 110 to transmit communication signals such as address, data, or control signals between processor 102 and other components in the system 100. The interface bus 110, in one embodiment, can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, processor busses are not limited to the DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI express), memory busses, or other types of interface busses. In one embodiment the processor(s) 102 include an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between a memory device and other components of the system 100, while the platform controller hub (PCH) 130 provides connections to I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device 120 can operate as system memory for the system 100, to store data 122 and instructions 121 for use when the one or more processors 102 executes an application or process. Memory controller 116 also couples with an optional external graphics processor 118, which may communicate with the one or more graphics processors 108 in processors 102 to perform graphics and media operations. In some embodiments, graphics, media, and or compute operations may be assisted by an accelerator 112 which is a coprocessor that can be configured to perform a specialized set of graphics, media, or compute operations. For example, in one embodiment the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or compute operations. In one embodiment the accelerator 112 is a ray-tracing accelerator that can be used to perform ray-tracing operations in concert with the graphics processor 108. In one embodiment, an external accelerator 119 may be used in place of or in concert with the accelerator 112.

In some embodiments a display device 111 can connect to the processor(s) 102. The display device 111 can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment the display device 111 can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In some embodiments the platform controller hub 130 enables peripherals to connect to memory device 120 and processor 102 via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, touch sensors 125, a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI express). The touch sensors 125 can include touch screen sensors, pressure sensors, or fingerprint sensors. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. The firmware interface 128 enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). The network controller 134 can enable a network connection to a wired network. In some embodiments, a high-performance network controller (not shown) couples with the interface bus 110. The audio controller 146, in one embodiment, is a multi-channel high definition audio controller. In one embodiment the system 100 includes an optional legacy I/O controller 140 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. The platform controller hub 130 can also connect to one or more Universal Serial Bus (USB) controllers 142 connect input devices, such as keyboard and mouse 143 combinations, a camera 144, or other USB input devices.

It will be appreciated that the system 100 shown is example and not limiting, as other types of data processing systems that are differently configured may also be used. For example, an instance of the memory controller 116 and platform controller hub 130 may be integrated into a discreet external graphics processor, such as the external graphics processor 118. In one embodiment the platform controller hub 130 and/or memory controller 116 may be external to the one or more processor(s) 102. For example, the system 100 can include an external memory controller 116 and platform controller hub 130, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with the processor(s) 102.

For example, circuit boards (“sleds”) can be used on which components such as CPUs, memory, and other components are placed are designed for increased thermal performance. In some examples, processing components such as the processors are located on a top side of a sled while near memory, such as DIMMs, are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Furthermore, the sleds are configured to blindly mate with power and data communication cables in a rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.

A data center can utilize a single network architecture (“fabric”) that supports multiple other network architectures including Ethernet and Omni-Path. The sleds can be coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center may, in use, pool resources, such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and/or artificial intelligence accelerators, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on a requested basis, enabling the compute resources to access the pooled resources as if they were local.

A power supply or source can provide voltage and/or current to system 100 or any component or system described herein. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source. In one example, power source includes a DC power source, such as an external AC to DC converter. In one example, power source or power supply includes wireless charging hardware to charge via proximity to a charging field. In one example, power source can include an internal battery, alternating current supply, motion-based power supply, solar power supply, or fuel cell source.

FIGS. 2A-2D illustrate computing systems and graphics processors provided by embodiments described herein. The elements of FIGS. 2A-2D having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

FIG. 2A is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. Processor 200 can include additional cores up to and including additional core 202N represented by the dashed lined boxes. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments each processor core also has access to one or more shared cached units 206. The internal cache units 204A-204N and shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI express busses. System agent core 210 provides management functionality for the various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multi-threading. In such embodiment, the system agent core 210 includes components for coordinating and operating cores 202A-202N during multi-threaded processing. System agent core 210 may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphics processor 208 to execute graphics processing operations. In some embodiments, the graphics processor 208 couples with the set of shared cache units 206, and the system agent core 210, including the one or more integrated memory controllers 214. In some embodiments, the system agent core 210 also includes a display controller 211 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 208.

In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of the processor 200. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor 208 couples with the ring interconnect 212 via an I/O link 213.

The example I/O link 213 represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and graphics processor 208 can use embedded memory modules 218 as a shared Last Level Cache.

In some embodiments, processor cores 202A-202N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 202A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 202A-202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. In one embodiment, processor cores 202A-202N are heterogeneous in terms of computational capability. Additionally, processor 200 can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

FIG. 2B is a block diagram of hardware logic of a graphics processor core 219, according to some embodiments described herein. Elements of FIG. 2B having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. The graphics processor core 219, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. The graphics processor core 219 is example of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 can include a fixed function block 230 coupled with multiple sub-cores 221A-221F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic.

In some embodiments, the fixed function block 230 includes a geometry/fixed function pipeline 231 that can be shared by all sub-cores in the graphics processor core 219, for example, in lower performance and/or lower power graphics processor implementations. In various embodiments, the geometry/fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., 3D pipeline 312 as in FIG. 3 and FIG. 4, described below) a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers (e.g., unified return buffer 418 in FIG. 4, as described below).

In one embodiment the fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores within a system on a chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that is configurable to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and pre-emption. The media pipeline 234 (e.g., media pipeline 316 of FIG. 3 and FIG. 4) includes logic to facilitate the decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipeline 234 implement media operations via requests to compute or sampling logic within the sub-cores 221-221F.

In one embodiment the SoC interface 232 enables the graphics processor core 219 to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, the system RAM, and/or embedded on-chip or on-package DRAM. The SoC interface 232 can also enable communication with fixed function devices within the SoC, such as camera imaging pipelines, and enables the use of and/or implements global memory atomics that may be shared between the graphics processor core 219 and CPUs within the SoC. The SoC interface 232 can also implement power management controls for the graphics processor core 219 and enable an interface between a clock domain of the graphic core 219 and other clock domains within the SoC. In one embodiment the SoC interface 232 enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions can be dispatched to the media pipeline 234, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 231, geometry and fixed function pipeline 237) when graphics processing operations are to be performed.

The graphics microcontroller 233 can be configured to perform various scheduling and management tasks for the graphics processor core 219. In one embodiment the graphics microcontroller 233 can perform graphics and/or compute workload scheduling on the various graphics parallel engines within execution unit (EU) arrays 222A-222F, 224A-224F within the sub-cores 221A-221F. In this scheduling model, host software executing on a CPU core of an SoC including the graphics processor core 219 can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In one embodiment the graphics microcontroller 233 can also facilitate low-power or idle states for the graphics processor core 219, providing the graphics processor core 219 with the ability to save and restore registers within the graphics processor core 219 across low-power state transitions independently from the operating system and/or graphics driver software on the system.

The graphics processor core 219 may have greater than or fewer than the illustrated sub-cores 221A-221F, up to N modular sub-cores. For each set of N sub-cores, the graphics processor core 219 can also include shared function logic 235, shared and/or cache memory 236, a geometry/fixed function pipeline 237, as well as additional fixed function logic 238 to accelerate various graphics and compute processing operations. The shared function logic 235 can include logic units associated with the shared function logic 420 of FIG. 4 (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within the graphics processor core 219. The shared and/or cache memory 236 can be a last-level cache for the set of N sub-cores 221A-221F within the graphics processor core 219, and can also serve as shared memory that is accessible by multiple sub-cores. The geometry/fixed function pipeline 237 can be included instead of the geometry/fixed function pipeline 231 within the fixed function block 230 and can include the same or similar logic units.

In one embodiment the graphics processor core 219 includes additional fixed function logic 238 that can include various fixed function acceleration logic for use by the graphics processor core 219. In one embodiment the additional fixed function logic 238 includes an additional geometry pipeline for use in position only shading. In position-only shading, two geometry pipelines exist, the full geometry pipeline within the geometry/fixed function pipeline 238, 231, and a cull pipeline, which is an additional geometry pipeline which may be included within the additional fixed function logic 238. In one embodiment the cull pipeline is a trimmed down version of the full geometry pipeline. The full pipeline and the cull pipeline can execute different instances of the same application, each instance having a separate context. Position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example and in one embodiment the cull pipeline logic within the additional fixed function logic 238 can execute position shaders in parallel with the main application and generally generates results faster than the full pipeline, as the cull pipeline fetches and shades only the position attribute of the vertices, without performing rasterization and rendering of the pixels to the frame buffer. The cull pipeline can use the generated results to compute visibility information for all the triangles without regard to whether those triangles are culled. The full pipeline (which in this instance may be referred to as a replay pipeline) can consume the visibility information to skip the culled triangles to shade only the visible triangles that are finally passed to the rasterization phase.

In one embodiment the additional fixed function logic 238 can also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing.

Within each graphics sub-core 221A-221F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. The graphics sub-cores 221A-221F include multiple EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD/IC) logic 223A-223F, a 3D (e.g., texture) sampler 225A-225F, a media sampler 206A-206F, a shader processor 227A-227F, and shared local memory (SLM) 228A-228F. The EU arrays 222A-222F, 224A-224F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. The TD/IC logic 223A-223F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitate communication between threads executing on the execution units of the sub-core. The 3D sampler 225A-225F can read texture or other 3D graphics related data into memory. The 3D sampler can read texture data differently based on a configured sample state and the texture format associated with a given texture. The media sampler 206A-206F can perform similar read operations based on the type and format associated with media data. In one embodiment, each graphics sub-core 221A-221F can alternately include a unified 3D and media sampler. Threads executing on the execution units within each of the sub-cores 221A-221F can make use of shared local memory 228A-228F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory.

FIG. 2C illustrates a graphics processing unit (GPU) 239 that includes dedicated sets of graphics processing resources arranged into multi-core groups 240A-240N. While the details of only a single multi-core group 240A are provided, it will be appreciated that the other multi-core groups 240B-240N may be equipped with the same or similar sets of graphics processing resources.

As illustrated, a multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. A scheduler/dispatcher 241 schedules and dispatches the graphics threads for execution on the various cores 243, 244, 245. A set of register files 242 store operand values used by the cores 243, 244, 245 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating point data elements) and tile registers for storing tensor/matrix values. In one embodiment, the tile registers are implemented as combined sets of vector registers.

One or more combined level 1 (L1) caches and shared memory units 247 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multi-core group 240A. One or more texture units 247 can also be used to perform texturing operations, such as texture mapping and sampling. A Level 2 (L2) cache 253 shared by all or a subset of the multi-core groups 240A-240N stores graphics data and/or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 253 may be shared across a plurality of multi-core groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to a memory 249 which may be a system memory (e.g., DRAM) and/or a dedicated graphics memory (e.g., GDDR6 memory).

Input/output (I/O) circuitry 250 couples the GPU 239 to one or more I/O devices 252 such as digital signal processors (DSPs), network controllers, or user input devices. An on-chip interconnect may be used to couple the I/O devices 252 to the GPU 239 and memory 249. One or more I/O memory management units (IOMMUs) 251 of the I/O circuitry 250 couple the I/O devices 252 directly to the system memory 249. In one embodiment, the IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, the I/O devices 252, CPU(s) 246, and GPU(s) 239 may share the same virtual address space.

In one implementation, the IOMMU 251 supports virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map the guest/graphics physical addresses to system/host physical addresses (e.g., within system memory 249). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out on a context switch (e.g., so that the new context is provided with access to the relevant set of page tables). While not illustrated in FIG. 2C, each of the cores 243, 244, 245 and/or multi-core groups 240A-240N may include translation lookaside buffers (TLBs) to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

In one embodiment, the CPUs 246, GPUs 239, and I/O devices 252 are integrated on a single semiconductor chip and/or chip package. The illustrated memory 249 may be integrated on the same chip or may be coupled to the memory controllers 248 via an off-chip interface. In one implementation, the memory 249 comprises GDDR6 memory which shares the same virtual address space as other physical system-level memories, although the underlying principles of the embodiments herein are not limited to this specific implementation.

In one embodiment, the tensor cores 244 include a plurality of execution units specifically designed to perform matrix operations, which are the base compute operation used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inferencing. The tensor cores 244 may perform matrix processing using a variety of operand precisions including single precision floating-point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half-bytes (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames, to construct a high-quality final image.

In deep learning implementations, parallel matrix multiplication work may be scheduled for execution on the tensor cores 244. The training of neural networks, in particular, utilizes a significant number matrix dot product operations. In order to process an inner-product formulation of an N×N×N matrix multiply, the tensor cores 244 may include at least N dot-product processing elements. Before the matrix multiply begins, one entire matrix is loaded into tile registers and at least one column of a second matrix is loaded each cycle for N cycles. Each cycle, there are N dot products that are processed.

Matrix elements may be stored at different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for the tensor cores 244 to ensure that the most efficient precision is used for different workloads (e.g., such as inferencing workloads which can tolerate quantization to bytes and half-bytes).

In one embodiment, the ray tracing cores 245 accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing cores 245 include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes. The ray tracing cores 245 may also include circuitry for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing cores 245 perform traversal and intersection operations in concert with the image denoising techniques described herein, at least a portion of which may be executed on the tensor cores 244. For example, in one embodiment, the tensor cores 244 implement a deep learning neural network to perform denoising of frames generated by the ray tracing cores 245. However, the CPU(s) 246, graphics cores 243, and/or ray tracing cores 245 may also implement all or a portion of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to denoising may be employed in which the GPU 239 is in a computing device coupled to other computing devices over a network or high speed interconnect. In this embodiment, the interconnected computing devices share neural network learning/training data to improve the speed with which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.

In one embodiment, the ray tracing cores 245 process all BVH traversal and ray-primitive intersections, saving the graphics cores 243 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, in one embodiment, the multi-core group 240A can simply launch a ray probe, and the ray tracing cores 245 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or compute work while the ray tracing cores 245 perform the traversal and intersection operations.

In one embodiment, each ray tracing core 245 includes a traversal unit to perform BVH testing operations and an intersection unit which performs ray-primitive intersection tests. The intersection unit generates a “hit”, “no hit”, or “multiple hit” response, which it provides to the appropriate thread. During the traversal and intersection operations, the execution resources of the other cores (e.g., graphics cores 243 and tensor cores 244) are freed to perform other forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/ray tracing approach is used in which work is distributed between the graphics cores 243 and ray tracing cores 245.

In one embodiment, the ray tracing cores 245 (and/or other cores 243, 244) include hardware support for a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR) which includes a DispatchRays command, as well as ray-generation, closest-hit, any-hit, and miss shaders, which enable the assignment of sets of shaders and textures for each object. Another ray tracing platform which may be supported by the ray tracing cores 245, graphics cores 243 and tensor cores 244 is Vulkan 1.1.85. Note, however, that the underlying principles of the embodiments herein are not limited to any particular ray tracing ISA.

In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes instructions/functions for ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions. More specifically, one embodiment includes ray tracing instructions to perform the following functions:

Ray Generation—Ray generation instructions may be executed for each pixel, sample, or other user-defined work assignment.

Closest Hit—A closest hit instruction may be executed to locate the closest intersection point of a ray with primitives within a scene.

Any Hit—An any hit instruction identifies multiple intersections between a ray and primitives within a scene, potentially to identify a new closest intersection point.

Intersection—An intersection instruction performs a ray-primitive intersection test and outputs a result.

Per-primitive Bounding box Construction—This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

Miss—Indicates that a ray misses all geometry within a scene, or specified region of a scene.

Visit—Indicates the children volumes a ray will traverse.

Exceptions—Includes various types of exception handlers (e.g., invoked for various error conditions).

FIG. 2D is a block diagram of general purpose graphics processing unit (GPGPU) 270 that can be configured as a graphics processor and/or compute accelerator, according to embodiments described herein. The GPGPU 270 can interconnect with host processors (e.g., one or more CPU(s) 246) and memory 271, 272 via one or more system and/or memory busses. In one embodiment the memory 271 is system memory that may be shared with the one or more CPU(s) 246, while memory 272 is device memory that is dedicated to the GPGPU 270. In one embodiment, components within the GPGPU 270 and device memory 272 may be mapped into memory addresses that are accessible to the one or more CPU(s) 246. Access to memory 271 and 272 may be facilitated via a memory controller 268. In one embodiment the memory controller 268 includes an internal direct memory access (DMA) controller 269 or can include logic to perform operations that would otherwise be performed by a DMA controller.

The GPGPU 270 includes multiple cache memories, including an L2 cache 253, L1 cache 254, an instruction cache 255, and shared memory 256, at least a portion of which may also be partitioned as a cache memory. The GPGPU 270 also includes multiple compute units 260A-260N. Each compute unit 260A-260N includes a set of vector registers 261, scalar registers 262, vector logic units 263, and scalar logic units 264. The compute units 260A-260N can also include local shared memory 265 and a program counter 266. The compute units 260A-260N can couple with a constant cache 267, which can be used to store constant data, which is data that will not change during the run of kernel or shader program that executes on the GPGPU 270. In one embodiment the constant cache 267 is a scalar data cache and cached data can be fetched directly into the scalar registers 262.

During operation, the one or more CPU(s) 246 can write commands into registers or memory in the GPGPU 270 that has been mapped into an accessible address space. The command processors 257 can read the commands from registers or memory and determine how those commands will be processed within the GPGPU 270. A thread dispatcher 258 can then be used to dispatch threads to the compute units 260A-260N to perform those commands. Each compute unit 260A-260N can execute threads independently of the other compute units. Additionally each compute unit 260A-260N can be independently configured for conditional computation and can conditionally output the results of computation to memory. The command processors 257 can interrupt the one or more CPU(s) 246 when the submitted commands are complete.

FIGS. 3A-3C illustrate block diagrams of additional graphics processor and compute accelerator architectures provided by embodiments described herein. The elements of FIGS. 3A-3C having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

FIG. 3A is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores, or other semiconductor devices such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor 300 includes a memory interface 314 to access memory. Memory interface 314 can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a display controller 302 to drive display output data to a display device 318. Display controller 302 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device 318 can be an internal or external display device. In one embodiment the display device 318 is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, H.265/HEVC, Alliance for Open Media (AOMedia) VP8, VP9, as well as the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system 315. While 3D pipeline 312 can be used to perform media operations, an embodiment of GPE 310 also includes a media pipeline 316 that is specifically used to perform media operations, such as video post-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine 306. In some embodiments, media pipeline 316 additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system 315. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executing threads spawned by 3D pipeline 312 and media pipeline 316. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

FIG. 3B illustrates a graphics processor 320 having a tiled architecture, according to embodiments described herein. In one embodiment the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A within a graphics engine tile 310A-310D. Each graphics engine tile 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D can also be connected to a memory module or memory device 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D can use any graphics memory technology. For example, the memory devices 326A-326D may be graphics double data rate (GDDR) memory. The memory devices 326A-326D, in one embodiment, are high-bandwidth memory (HBM) modules that can be on-die with their respective graphics engine tile 310A-310D. In one embodiment the memory devices 326A-326D are stacked memory devices that can be stacked on top of their respective graphics engine tile 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D reside on separate chiplets, which are bonded to a base die or base substrate, as described on further detail in FIGS. 11B-11D.

The graphics processor 320 may be configured with a non-uniform memory access (NUMA) systemin which memory devices 326A-326D are coupled with associated graphics engine tiles 310A-310D. A given memory device may be accessed by graphics engine tiles other than the tile to which it is directly connected. However, access latency to the memory devices 326A-326D may be lowest when accessing a local tile. In one embodiment, a cache coherent NUMA (ccNUMA) system is enabled that uses the tile interconnects 323A-323F to enable communication between cache controllers within the graphics engine tiles 310A-310D to keep a consistent memory image when more than one cache stores the same memory location.

The graphics processing engine cluster 322 can connect with an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 can enable communication between graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engines 304 can be used to move data out of, into, and between the memory devices 326A-326D and memory that is external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 can also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable a connection with an external display device 318. The graphics processor may also be configured as a graphics or compute accelerator. In the accelerator configuration, the display controller 302 and display device 318 may be omitted.

The graphics processor 320 can connect to a host system via a host interface 328. The host interface 328 can enable communication between the graphics processor 320, system memory, and/or other system components. The host interface 328 can be, for example a PCI express bus or another type of host system interface.

FIG. 3C illustrates a compute accelerator 330, according to embodiments described herein. The compute accelerator 330 can include architectural similarities with the graphics processor 320 of FIG. 3B and is optimized for compute acceleration. A compute engine cluster 332 can include a set of compute engine tiles 340A-340D that include execution logic that is optimized for parallel or vector-based general-purpose compute operations. In some embodiments, the compute engine tiles 340A-340D do not include fixed function graphics processing logic, although in one embodiment one or more of the compute engine tiles 340A-340D can include logic to perform media acceleration. The compute engine tiles 340A-340D can connect to memory 326A-326D via memory interconnects 325A-325D. The memory 326A-326D and memory interconnects 325A-325D may be similar technology as in graphics processor 320, or can be different. The graphics compute engine tiles 340A-340D can also be interconnected via a set of tile interconnects 323A-323F and may be connected with and/or interconnected by a fabric interconnect 324. In one embodiment the compute accelerator 330 includes a large L3 cache 336 that can be configured as a device-wide cache. The compute accelerator 330 can also connect to a host processor and memory via a host interface 328 in a similar manner as the graphics processor 320 of FIG. 3B.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A, and may also represent a graphics engine tile 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and media pipeline 316 of FIG. 3A are illustrated. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example and in at least one embodiment, a separate media and/or image processor is coupled to the GPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer 403, which provides a command stream to the 3D pipeline 312 and/or media pipelines 316. In some embodiments, command streamer 403 is coupled with memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 403 receives commands from the memory and sends the commands to 3D pipeline 312 and/or media pipeline 316. The commands are directives fetched from a ring buffer, which stores commands for the 3D pipeline 312 and media pipeline 316. In one embodiment, the ring buffer can additionally include batch command buffers storing batches of multiple commands. The commands for the 3D pipeline 312 can also include references to data stored in memory, such as but not limited to vertex and geometry data for the 3D pipeline 312 and/or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and media pipeline 316 process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to a graphics core array 414. In one embodiment the graphics core array 414 include one or more blocks of graphics cores (e.g., graphics core(s) 415A, graphics core(s) 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline 312 can include fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing the instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. Multi-purpose execution logic (e.g., execution units) within the graphics core(s) 415A-414B of the graphic core array 414 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

In some embodiments, the graphics core array 414 includes execution logic to perform media functions, such as video and/or image processing. In one embodiment, the execution units include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general-purpose logic within the processor core(s) 107 of FIG. 1 or core 202A-202N as in FIG. 2A.

Output data generated by threads executing on the graphics core array 414 can output data to memory in a unified return buffer (URB) 418. The URB 418 can store data for multiple threads. In some embodiments the URB 418 may be used to send data between different threads executing on the graphics core array 414. In some embodiments the URB 418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 420.

In some embodiments, graphics core array 414 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment the execution resources are dynamically scalable, such that execution resources may be enabled or disabled.

The graphics core array 414 couples with shared function logic 420 that includes multiple resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 420 are hardware logic units that provide specialized supplemental functionality to the graphics core array 414. In various embodiments, shared function logic 420 includes but is not limited to sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more cache(s) 425 within the shared function logic 420.

A shared function is implemented at least in a case where the demand for a given specialized function is insufficient for inclusion within the graphics core array 414. Instead a single instantiation of that specialized function is implemented as a stand-alone entity in the shared function logic 420 and shared among the execution resources within the graphics core array 414. The precise set of functions that are shared between the graphics core array 414 and included within the graphics core array 414 varies across embodiments. In some embodiments, specific shared functions within the shared function logic 420 that are used extensively by the graphics core array 414 may be included within shared function logic 416 within the graphics core array 414. In various embodiments, the shared function logic 416 within the graphics core array 414 can include some or all logic within the shared function logic 420. In one embodiment, all logic elements within the shared function logic 420 may be duplicated within the shared function logic 416 of the graphics core array 414. In one embodiment the shared function logic 420 is excluded in favor of the shared function logic 416 within the graphics core array 414.

Execution Units

FIGS. 5A-5B illustrate thread execution logic 500 including an array of processing elements employed in a graphics processor core according to embodiments described herein. Elements of FIGS. 5A-5B having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. FIG. 5A-5B illustrates an overview of thread execution logic 500, which may be representative of hardware logic illustrated with each sub-core 221A-221F of FIG. 2B. FIG. 5A is representative of an execution unit within a general-purpose graphics processor, while FIG. 5B is representative of an execution unit that may be used within a compute accelerator.

As illustrated in FIG. 5A, in some embodiments thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, instruction cache 506, a scalable execution unit array including a plurality of execution units 508A-508N, a sampler 510, shared local memory 511, a data cache 512, and a data port 514. In one embodiment the scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D, through 508N-1 and 508N) based on the computational requirements of a workload. In one embodiment the included components are interconnected via an interconnect fabric that links to each of the components. In some embodiments, thread execution logic 500 includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache 506, data port 514, sampler 510, and execution units 508A-508N. In some embodiments, each execution unit (e.g. 508A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number individual execution units.

In some embodiments, the execution units 508A-508N are primarily used to execute shader programs. A shader processor 502 can process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher 504. In one embodiment the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution units 508A-508N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. In some embodiments, thread dispatcher 504 can also process runtime thread spawning requests from the executing shader programs.

In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). Each of the execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units 508A-508N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader. Various embodiments can apply to use execution by use of Single Instruction Multiple Thread (SIMT) as an alternate to use of SIMD or in addition to use of SIMD. Reference to a SIMD core or operation can apply also to SIMT or apply to SIMD in combination with SIMT.

Each execution unit in execution units 508A-508N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating-point data types.

The execution unit instruction set includes SIMD instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 54-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into a fused execution unit 509A-509N having thread control logic (507A-507N) that is common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to embodiments. Additionally, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, fused execution unit 509A includes a first EU 508A, second EU 508B, and thread control logic 507A that is common to the first EU 508A and the second EU 508B. The thread control logic 507A controls threads executed on the fused graphics execution unit 509A, allowing each EU within the fused execution units 509A-509N to execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included to cache thread data during thread execution. Threads executing on the execution logic 500 can also store explicitly managed data in the shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 510 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send thread initiation requests to thread execution logic 500 via thread spawning and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 502 is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, a pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some embodiments, pixel processor logic within the shader processor 502 then executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, the shader processor 502 dispatches threads to an execution unit (e.g., 508A) via thread dispatcher 504. In some embodiments, shader processor 502 uses texture sampling logic in the sampler 510 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.

In some embodiments, the data port 514 provides a memory access mechanism for the thread execution logic 500 to output processed data to memory for further processing on a graphics processor output pipeline. In some embodiments, the data port 514 includes or couples to one or more cache memories (e.g., data cache 512) to cache data for memory access via the data port.

In one embodiment, the execution logic 500 can also include a ray tracer 505 that can provide ray tracing acceleration functionality. The ray tracer 505 can support a ray tracing instruction set that includes instructions/functions for ray generation. The ray tracing instruction set can be similar to or different from the ray-tracing instruction set supported by the ray tracing cores 245 in FIG. 2C.

FIG. 5B illustrates example internal details of an execution unit 508, according to embodiments. A graphics execution unit 508 can include an instruction fetch unit 537, a general register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD floating point units (FPUs) 534, and in one embodiment a set of dedicated integer SIMD ALUs 535. The GRF 524 and ARF 526 includes the set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in the graphics execution unit 508. In one embodiment, per thread architectural state is maintained in the ARF 526, while data used during thread execution is stored in the GRF 524. The execution state of each thread, including the instruction pointers for each thread, can be held in thread-specific registers in the ARF 526.

In one embodiment the graphics execution unit 508 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads. The number of logical threads that may be executed by the graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

In one embodiment, the graphics execution unit 508 can co-issue multiple instructions, which may each be different instructions. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch the instructions to one of the send unit 530, branch unit 532, or SIMD FPU(s) 534 for execution. Each execution thread can access 128 general-purpose registers within the GRF 524, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4 Kbytes within the GRF 524, although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In one embodiment the graphics execution unit 508 is partitioned into seven hardware threads that can independently perform computational operations, although the number of threads per execution unit can also vary according to embodiments. For example, in one embodiment up to 16 hardware threads are supported. In an embodiment in which seven threads may access 4 Kbytes, the GRF 524 can store a total of 28 Kbytes. Where 16 threads may access 4 Kbytes, the GRF 524 can store a total of 64 Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.

In one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by the message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit 508 includes one or more SIMD floating point units (FPU(s)) 534 to perform floating-point operations. In one embodiment, the FPU(s) 534 also support integer computation. In one embodiment the FPU(s) 534 can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 54-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present, and may be specifically optimized to perform operations associated with machine learning computations.

In one embodiment, arrays of multiple instances of the graphics execution unit 508 can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can choose the exact number of execution units per sub-core grouping. In one embodiment the execution unit 508 can execute instructions across a plurality of execution channels. In a further embodiment, each thread executed on the graphics execution unit 508 is executed on a different channel.

FIG. 6 illustrates an additional execution unit 600, according to an embodiment. The execution unit 600 may be a compute-optimized execution unit for use in, for example, a compute engine tile 340A-340D as in FIG. 3C, but is not limited as such. Variants of the execution unit 600 may also be used in a graphics engine tile 310A-310D as in FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch/prefetch unit 603, and an instruction decode unit 604 (also referred to herein as a decoder). The execution unit 600 additionally includes a register file 606 that stores registers that can be assigned to hardware threads within the execution unit. The execution unit 600 additionally includes a send unit 607 and a branch unit 608. In one embodiment, the send unit 607 and branch unit 608 can operate similarly as the send unit 530 and a branch unit 532 of the graphics execution unit 508 of FIG. 5B.

The execution unit 600 also includes a compute unit 610 that includes multiple different types of functional units. In one embodiment the compute unit 610 includes an ALU unit 611 that includes an array of arithmetic logic units. The ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. Integer and floating point operations may be performed simultaneously. The compute unit 610 can also include a systolic array 612, and a math unit 613. The systolic array 612 includes a W wide and D deep network of data processing units that can be used to perform vector or other data-parallel operations in a systolic manner. In one embodiment the systolic array 612 can be configured to perform matrix operations, such as matrix dot product operations. In one embodiment the systolic array 612 support 16-bit floating point operations, as well as 8-bit and 4-bit integer operations. In one embodiment the systolic array 612 can be configured to accelerate machine learning operations. In such embodiments, the systolic array 612 can be configured with support for the bfloat 16-bit floating point format. In one embodiment, a math unit 613 can be included to perform a specific subset of mathematical operations in an efficient and lower-power manner than then ALU unit 611. The math unit 613 can include a variant of math logic that may be found in shared function logic of a graphics processing engine provided by other embodiments (e.g., math logic 422 of the shared function logic 420 of FIG. 4). In one embodiment the math unit 613 can be configured to perform 32-bit and 64-bit floating point operations.

The thread control unit 601 includes logic to control the execution of threads within the execution unit. The thread control unit 601 can include thread arbitration logic to start, stop, and preempt execution of threads within the execution unit 600. The thread state unit 602 can be used to store thread state for threads assigned to execute on the execution unit 600. Storing the thread state within the execution unit 600 enables the rapid pre-emption of threads when those threads become blocked or idle. The instruction fetch/prefetch unit 603 can fetch instructions from an instruction cache of higher level execution logic (e.g., instruction cache 506 as in FIG. 5A). The instruction fetch/prefetch unit 603 can also issue prefetch requests for instructions to be loaded into the instruction cache based on an analysis of currently executing threads. The instruction decode unit 604 can be used to decode instructions to be executed by the compute units. In one embodiment, the instruction decode unit 604 can be used as a secondary decoder to decode complex instructions into constituent micro-operations.

The execution unit 600 additionally includes a register file 606 that can be used by hardware threads executing on the execution unit 600. Registers in the register file 606 can be divided across the logic used to execute multiple simultaneous threads within the compute unit 610 of the execution unit 600. The number of logical threads that may be executed by the graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of the register file 606 can vary across embodiments based on the number of supported hardware threads. In one embodiment, register renaming may be used to dynamically allocate registers to hardware threads.

FIG. 7 is a block diagram illustrating a graphics processor instruction formats 700 according to some embodiments. In one or more embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some embodiments, instruction format 700 described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed.

In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format 710. A 64-bit compacted instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 730. The native instructions available in the 64-bit format 730 vary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field 713. The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format 710. Other sizes and formats of instruction can be used.

For each format, instruction opcode 712 defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some embodiments, instruction control field 714 enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710 an exec-size field 716 limits the number of data channels that will be executed in parallel. In some embodiments, exec-size field 716 is not available for use in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2 724), where the instruction opcode 712 determines the number of source operands. An instruction's last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.

In some embodiments, the 128-bit instruction format 710 includes an access/address mode field 726 specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes an access/address mode field 726, which specifies an address mode and/or an access mode for the instruction. In one embodiment the access mode is used to define a data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

In one embodiment, the address mode portion of the access/address mode field 726 determines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712 bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, a move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group 742 shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 748 performs the arithmetic operations in parallel across data channels. The vector math group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. The illustrated opcode decode 740, in one embodiment, can be used to determine which portion of an execution unit will be used to execute a decoded instruction. For example, some instructions may be designated as systolic instructions that will be performed by a systolic array. Other instructions, such as ray-tracing instructions (not shown) can be routed to a ray-tracing core or ray-tracing logic within a slice or partition of execution logic.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor 800. Elements of FIG. 8 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a render output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by a command streamer 803, which supplies instructions to individual components of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of a vertex fetcher 805 that reads vertex data from memory and executes vertex-processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides vertex data to a vertex shader 807, which performs coordinate space transformation and lighting operations to each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex-processing instructions by dispatching execution threads to execution units 852A-852B via a thread dispatcher 831.

In some embodiments, execution units 852A-852B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 852A-852B have an attached L1 cache 851 that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of tessellation output. A tessellator 813 operates at the direction of hull shader 811 and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to geometry pipeline 820. In some embodiments, if tessellation is not used, tessellation components (e.g., hull shader 811, tessellator 813, and domain shader 817) can be bypassed. The tessellation components can operate based on data received from the vertex shader 807.

In some embodiments, complete geometric objects can be processed by a geometry shader 819 via one or more threads dispatched to execution units 852A-852B, or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader 819 receives input from the vertex shader 807. In some embodiments, geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper 829 may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 in the render output pipeline 870 dispatches pixel shaders to convert the geometric objects into per pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via a data port 856 to perform memory access and communicate with render output pipeline components of the processor. In some embodiments, sampler 854, caches 851, 858 and execution units 852A-852B each have separate memory access paths. In one embodiment the texture cache 858 can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache 878 and depth cache 879 are also available in some embodiments. A pixel operations component 877 performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine 841, or substituted at display time by the display controller 843 using overlay display planes. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing the sharing of data without the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes a media engine 837 and a video front-end 834. In some embodiments, video front-end 834 receives pipeline commands from the command streamer 803. In some embodiments, media pipeline 830 includes a separate command streamer. In some embodiments, video front-end 834 processes media commands before sending the command to the media engine 837. In some embodiments, media engine 837 includes thread spawning functionality to spawn threads for dispatch to thread execution logic 850 via thread dispatcher 831.

In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples with the graphics processor via the ring interconnect 802, or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 contains special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controller 843 couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.

In some embodiments, the geometry pipeline 820 and media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or Vulkan graphics and compute API, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from the Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. FIG. 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. The solid lined boxes in FIG. 9A illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The example graphics processor command format 900 of FIG. 9A includes data fields to identify a client 902, a command operation code (opcode) 904, and data 906 for the command. A sub-opcode 905 and a command size 908 are also included in some commands.

In some embodiments, client 902 specifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcode 904 and, if present, sub-opcode 905 to determine the operation to perform. The client unit performs the command using information in data field 906. For some commands an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word. Other command formats can be used.

The flow diagram in FIG. 9B illustrates an example graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some embodiments, pipeline flush command 912 can be used for pipeline synchronization or before placing the graphics processor into a low power state.

In some embodiments, a pipeline select command 913 is used when a command sequence utilizes the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command 913 is utilized once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 912 is utilized immediately before a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures a graphics pipeline for operation and is used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control command 914 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 914 is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations utilize the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination 920, the command sequence is tailored to the 3D pipeline 922 beginning with the 3D pipeline state 930 or the media pipeline 924 beginning at the media pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, 3D pipeline state 930 commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive 932 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 932 command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline 922 dispatches shader execution threads to graphics processor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations.

In some embodiments, the graphics processor command sequence 910 follows the media pipeline 924 path when performing media operations. In general, the specific use and manner of programming for the media pipeline 924 depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similar manner as the 3D pipeline 922. A set of commands to configure the media pipeline state 940 are dispatched or placed into a command queue before the media object commands 942. In some embodiments, commands for the media pipeline state 940 include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some embodiments, commands for the media pipeline state 940 also support the use of one or more pointers to “indirect” state elements that contain a batch of state settings.

In some embodiments, media object commands 942 supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some embodiments, all media pipeline states should be valid before issuing a media object command 942. Once the pipeline state is configured and media object commands 942 are queued, the media pipeline 924 is triggered via an execute command 944 or an equivalent execute event (e.g., register write). Output from media pipeline 924 may then be post processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates an example graphics software architecture for a data processing system 1000 according to some embodiments. In some embodiments, software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes a graphics processor 1032 and one or more general-purpose processor core(s) 1034. The graphics application 1010 and operating system 1020 each execute in the system memory 1050 of the data processing system.

In some embodiments, 3D graphics application 1010 contains one or more shader programs including shader instructions 1012. The shader language instructions may be in a high-level shader language, such as the High-Level Shader Language (HLSL) of Direct3D, the OpenGL Shader Language (GLSL), and so forth. The application also includes executable instructions 1014 in a machine language suitable for execution by the general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system 1020 can support a graphics API 1022 such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-end shader compiler 1027 to convert the shader instructions 1012 into a hardware specific representation. When the OpenGL API is in use, shader instructions 1012 in the GLSL high-level language are passed to a user mode graphics driver 1026 for compilation. In some embodiments, user mode graphics driver 1026 uses operating system kernel mode functions 1028 to communicate with a kernel mode graphics driver 1029. In some embodiments, kernel mode graphics driver 1029 communicates with graphics processor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. In some embodiments, the machine-readable medium is also referred to herein as a computer-readable medium or a non-transitory computer-readable medium. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

FIG. 11A is a block diagram illustrating an IP core development system 1100 that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 1100 may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility 1130 can generate a software simulation 1110 of an IP core design in a high-level programming language (e.g., C/C++). The software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and/or timing simulations. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design 1115, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3^(rd) party fabrication facility 1165 using non-volatile memory 1140 (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection 1150 or wireless connection 1160. The fabrication facility 1165 may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

FIG. 11B illustrates a cross-section side view of an integrated circuit package assembly 1170, according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic 1172, 1174 can be implemented within a semiconductor die and coupled with the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1170 can be connected to other electrical devices via a package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electrically coupled with a bridge 1182 that is configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a dense interconnect structure that provides a route for electrical signals. The bridge 1182 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic 1172, 1174.

Although two units of logic 1172, 1174 and a bridge 1182 are illustrated, embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as the bridge 1182 may be excluded when the logic is included on a single die. Alternatively, multiple dies or units of logic can be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

FIG. 11C illustrates a package assembly 1190 that includes multiple units of hardware logic chiplets connected to a substrate 1180 (e.g., base die). A graphics processing unit, parallel processor, and/or compute accelerator as described herein can be composed from diverse silicon chiplets that are separately manufactured. In this context, a chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device. Additionally the chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable the interconnection and communication between the different forms of IP within the GPU. IP cores can be manufactured using different process technologies and composed during manufacturing, which avoids the complexity of converging multiple IPs, especially on a large SoC with several flavors IPs, to the same manufacturing process. Enabling the use of multiple process technologies improves the time to market and provides a cost-effective way to create multiple product SKUs. Additionally, the disaggregated IPs are more amenable to being power gated independently, components that are not in use on a given workload can be powered off, reducing overall power consumption.

The hardware logic chiplets can include special purpose hardware logic chiplets 1172, logic or I/O chiplets 1174, and/or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I/O chiplets 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware and can include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplets 1175 can be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

Each chiplet can be fabricated as separate semiconductor die and coupled with the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the various chiplets and logic within the substrate 1180. The interconnect structure 1173 can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic, I/O and memory chiplets.

In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1190 can be connected to other electrical devices via a package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

In some embodiments, a logic or I/O chiplet 1174 and a memory chiplet 1175 can be electrically coupled via a bridge 1187 that is configured to route electrical signals between the logic or I/O chiplet 1174 and a memory chiplet 1175. The bridge 1187 may be a dense interconnect structure that provides a route for electrical signals. The bridge 1187 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic or I/O chiplet 1174 and a memory chiplet 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 1187, in some embodiments, is an Embedded Multi-die Interconnect Bridge (EMIB). In some embodiments, the bridge 1187 may simply be a direct connection from one chiplet to another chiplet.

The substrate 1180 can include hardware components for I/O 1191, cache memory 1192, and other hardware logic 1193. A fabric 1185 can be embedded in the substrate 1180 to enable communication between the various logic chiplets and the logic 1191, 1193 within the substrate 1180. In one embodiment, the I/O 1191, fabric 1185, cache, bridge, and other hardware logic 1193 can be integrated into a base die that is layered on top of the substrate 1180. The fabric 1185 may be a network on a chip interconnect or another form of packet switched fabric that switches data packets between components of the package assembly.

In various embodiments a package assembly 1190 can include fewer or greater number of components and chiplets that are interconnected by a fabric 1185 or one or more bridges 1187. The chiplets within the package assembly 1190 may be arranged in a 3D or 2.5D arrangement. In general, bridge structures 1187 may be used to facilitate a point to point interconnect between, for example, logic or I/O chiplets and memory chiplets. The fabric 1185 can be used to interconnect the various logic and/or I/O chiplets (e.g., chiplets 1172, 1174, 1191, 1193). with other logic and/or I/O chiplets. In one embodiment, the cache memory 1192 within the substrate can act as a global cache for the package assembly 1190, part of a distributed global cache, or as a dedicated cache for the fabric 1185.

FIG. 11D illustrates a package assembly 1194 including interchangeable chiplets 1195, according to an embodiment. The interchangeable chiplets 1195 can be assembled into standardized slots on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to the other bridge interconnects described herein and may be, for example, an EMIB. Memory chiplets can also be connected to logic or I/O chiplets via a bridge interconnect. I/O and logic chiplets can communicate via an interconnect fabric. The base chiplets can each support one or more slots in a standardized format for one of logic or I/O or memory/cache.

In one embodiment, SRAM and power delivery circuits can be fabricated into one or more of the base chiplets 1196, 1198, which can be fabricated using a different process technology relative to the interchangeable chiplets 1195 that are stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 can be fabricated using a larger process technology, while the interchangeable chiplets can be manufactured using a smaller process technology. One or more of the interchangeable chiplets 1195 may be memory (e.g., DRAM) chiplets. Different memory densities can be selected for the package assembly 1194 based on the power, and/or performance targeted for the product that uses the package assembly 1194. Additionally, logic chiplets with a different number of type of functional units can be selected at time of assembly based on the power, and/or performance targeted for the product. Additionally, chiplets containing IP logic cores of differing types can be inserted into the interchangeable chiplet slots, enabling hybrid processor designs that can mix and match different technology IP blocks.

Example System on a Chip Integrated Circuit

FIGS. 12-13B illustrate example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores.

FIG. 12 is a block diagram illustrating an example system on a chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment. Example integrated circuit 1200 includes one or more application processor(s) 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and/or a video processor 1220, any of which may be a modular IP core from the same or multiple different design facilities. Integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, UART controller 1230, an SPI/SDIO controller 1235, and an I²S/I²C controller 1240. Additionally, the integrated circuit can include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller. Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270.

FIGS. 13A-13B are block diagrams illustrating example graphics processors for use within an SoC, according to embodiments described herein. FIG. 13A illustrates an example graphics processor 1310 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 13B illustrates an additional example graphics processor 1340 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. Graphics processor 1310 of FIG. 13A is an example of a low power graphics processor core. Graphics processor 1340 of FIG. 13B is an example of a higher performance graphics processor core. Each of the graphics processors 1310, 1340 can be variants of the graphics processor 1210 of FIG. 12.

As shown in FIG. 13A, graphics processor 1310 includes a vertex processor 1305 and one or more fragment processor(s) 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphics processor 1310 can execute different shader programs via separate logic, such that the vertex processor 1305 is optimized to execute operations for vertex shader programs, while the one or more fragment processor(s) 1315A-1315N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to produce a framebuffer that is displayed on a display device. In one embodiment, the fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in the Direct 3D API.

Graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B provide for virtual to physical address mapping for the graphics processor 1310, including for the vertex processor 1305 and/or fragment processor(s) 1315A-1315N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in the one or more cache(s) 1325A-1325B. In one embodiment the one or more MMU(s) 1320A-1320B may be synchronized with other MMUs within the system, including one or more MMUs associated with the one or more application processor(s) 1205, image processor 1215, and/or video processor 1220 of FIG. 12, such that each processor 1205-1220 can participate in a shared or unified virtual memory system. The one or more circuit interconnect(s) 1330A-1330B enable graphics processor 1310 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection, according to embodiments.

As shown FIG. 13B, graphics processor 1340 includes the one or more MMU(s) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B of the graphics processor 1310 of FIG. 13A. Graphics processor 1340 includes one or more shader core(s) 1355A-1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present can vary among embodiments and implementations. Additionally, graphics processor 1340 includes an inter-core task manager 1345, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N and a tiling unit 1358 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

In some embodiments, a processing resource represents a processing element (e.g., GPGPU core, ray-tracing core, tensor core, execution resource, execution unit (EU), stream processor, streaming multiprocessor (SM), graphics multiprocessor) associated with a graphics processor or graphics processor structure (e.g., parallel processing unit, graphics processing engine, multi-core group, compute unit, compute unit of graphics core next) in a GPU as described herein. For example, the processing resource may be one of the GPGPU cores, or tensor/ray-tracing cores of graphics multiprocessor; a ray-tracing core, tensor core or GPGPU core of graphics multiprocessor; execution resources of graphics multiprocessor; one of GFX cores, tensor cores, or ray tracing cores of a multi-core group; one of vector logic units or scalar logic units of a compute unit; execution unit with EU array or EU array; an execution unit of execution logic; and/or execution unit. The processing resource may also be an execution resource within, for example, a graphics processing engine, processing cluster, GPGPU, GPGPU, graphics processing engine, graphics processing engine cluster, and/or graphics processing engine. The processing resource may also be a processing resource within graphics processor, graphics processor, and/or graphics processor.

Supporting 8-Bit Floating Point Format Operands in a Computing Architecture

Parallel computing is a type of computation in which many calculations or the execution of processes are carried out simultaneously. Parallel computing may come in a variety of forms, including, but not limited to, SIMD or SIMT. SIMD describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously. In one example, FIGS. 5A-5B discussed above refer to SIMD and its implementation in a general processor in terms of EUs, FPUs, and ALUs. In a common SIMD machine, data is packaged into registers, each containing an array of channels. Instructions operate on the data found in channel n of a register with the data found in the same channel of another register. SIMD machines are advantageous in areas where a single sequence of instructions can be simultaneously applied to high amounts of data. For example, in one embodiment, a graphics processor (e.g., GPGPU, GPU, etc.) can be used to perform SIMD vector operations using computational shader programs.

Various embodiments can also apply to use execution by use of Single Instruction Multiple Thread (SIMT) as an alternate to use of SIMD or in addition to use of SIMD. Reference to a SIMD core or operation can apply also to SIMT or apply to SIMD in combination with SIMT. The following description is discussed in terms of SIMD machines. However, embodiments herein are not solely limited to application in the SIMD context and may apply in other parallel computing paradigms, such as SIMT, for example. For ease of discussion and explanation, the following description generally focuses on a SIMD implementation. However, embodiments can similarly apply to SIMT machines with no modifications to the described techniques and methodologies. With respect to SIMT machines, similar patterns as discussed below can be followed to provide instructions to the systolic array and execute the instructions on the SIMT machine. Other types of parallel computing machines may also utilize embodiments herein as well.

Various embodiments can implement GPGPUs with matrix acceleration circuitry. Such matrix acceleration circuitry can be utilized for machine learning (ML) operation acceleration.

FIG. 14 is a block diagram of a data processing system 1400, according to an embodiment. Various embodiments discussed herein may be implemented in a system such as data processing system 1400. The data processing system 1400 is a heterogeneous processing system having a processor 1402, unified memory 1410, and a GPGPU 1420 including machine learning acceleration logic. The processor 1402 and the GPGPU 1420 can be any of the processors and GPGPU/parallel processors as described herein. The processor 1402 can execute instructions for a compiler 1415 stored in system memory 1412. The compiler 1415 executes on the processor 1402 to compile source code 1414A into compiled code 1414B. The compiled code 1414B can include instructions that may be executed by the processor 1402 and/or instructions that may be executed by the GPGPU 1420. During compilation, the compiler 1415 can perform operations to insert metadata, including hints as to the level of data parallelism present in the compiled code 1414B and/or hints regarding the data locality associated with threads to be dispatched based on the compiled code 1414B. The compiler 1415 can include the information utilized to perform such operations or the operations can be performed with the assistance of a runtime library 1416. The runtime library 1416 can also assist the compiler 1415 in the compilation of the source code 1414A and can also include instructions that are linked at runtime with the compiled code 1414B to facilitate execution of the compiled instructions on the GPGPU 1420.

The unified memory 1410 represents a unified address space that may be accessed by the processor 1402 and the GPGPU 1420. The unified memory can include system memory 1412 as well as GPGPU memory 1418. The GPGPU memory 1418 is memory within an address pace of the GPGPU 1420 and can include some or all of system memory 1412. In one embodiment the GPGPU memory 1418 can also include at least a portion of any memory dedicated for use by the GPGPU 1420. In one embodiment, compiled code 1414B stored in system memory 1412 can be mapped into GPGPU memory 1418 for access by the GPGPU 1420.

The GPGPU 1420 includes multiple compute blocks 1424A-1424N, which can include one or more of a variety of compute units or execution elements described herein. In one embodiment the GPGPU 1420 additionally includes a matrix accelerator 1423, which can include one or more special function compute units that are designed to accelerate a subset of matrix operations (e.g., dot product, etc.). The GPGPU 1420 can also include a set of resources that can be shared by the compute blocks 1424A-1424N and the matrix accelerator 1423, including but not limited to a set of registers 1425, a power and performance module 1426, and a cache 1427. In one embodiment the registers 1425 include directly and indirectly accessible registers, where the indirectly accessible registers are optimized for use by the matrix accelerator 1423. The power and performance module 1426 can be configured to adjust power delivery and clock frequencies for the compute blocks 1424A-1424N to power gate idle components within the compute blocks 1424A-1424N. In various embodiments the cache 1427 can include an instruction cache and/or a lower level data cache. [0148] The GPGPU 1420 can additionally include an L3 data cache 1430, which can be used to cache data accessed from the unified memory 1410 by the matrix accelerator 1423 and/or the compute elements within the compute blocks 1424A-1424N. In one embodiment the L3 data cache 1430 includes shared local memory 1432 that can be shared by the compute elements within the compute blocks 1424A-1424N and the matrix accelerator 1423.

In one embodiment the GPGPU 1420 includes instruction handling logic, such as a fetch and decode unit 1421 (also referred to herein as a decoder, such a decoder 1421) and a scheduler controller 1422. The fetch and decode unit 1421 includes a fetch unit and decode unit to fetch and decode instructions for execution by one or more of the compute blocks 1424A-1424N or the matrix accelerator 1423. The instructions can be scheduled to the appropriate functional unit within the compute block 1424A-1424N or the matrix accelerator via the scheduler controller 1422. In one embodiment the scheduler controller 1422 is an ASIC configurable to perform advanced scheduling operations. In one embodiment the scheduler controller 1422 is a microcontroller or a low energy-per-instruction processing core capable of executing scheduler instructions loaded from a firmware module.

In one embodiment some functions to be performed by the compute blocks 1424A-1424N can be directly scheduled to or offloaded to the matrix accelerator 1423. In various embodiments the matrix accelerator 1423 includes processing element logic configured to efficiently perform matrix compute operations, such as multiply and add operations and dot product operations used by 3D graphics or compute shader programs. In one embodiment the matrix accelerator 1423 can be configured to accelerate operations used by machine learning frameworks. In one embodiment the matrix accelerator 1423 is an application specific integrated circuit explicitly configured to perform a specific set of parallel matrix multiplication and/or addition operations. In one embodiment the matrix accelerator 1423 is a field programmable gate array (FPGA) that provides fixed function logic that can updated between workloads. The set of matrix operations that can be performed by the matrix accelerator 1423 may be limited relative to the operations that can be performed by the compute block 1424A-1424N. However, the matrix accelerator 1423 can perform those the operations at a significantly higher throughput relative to the compute block 1424A-1424N.

In embodiments, the data processing system 1400 of FIG. 14 may be utilized for applications in the fields of artificial intelligence (AI) and machine learning (ML). Advances in these fields have enabled ML models to take advantage of low-precision arithmetic for training neural network. Conventional training platforms support IEEE-754 floating point 16 (FP16) and brain floating point 16 (bfloat16 or BF16) data formats in high-performance systolic array implementations. However, recent advances have been made to support training of deep neural networks using lower precision data formats, such as an 8-bit floating point data format. One such 8-bit floating point data format is bfloat8 or BF8. The BF8 has a binary format of 1 sign bit, 5 exponent bits, and 2 mantissa bits. In some cases, utilizing the BF8 format can provide up to 2× improvement in training throughput of neural networks, as compared to a FP16 or BF16 implementation. However, conventional systems provide no hardware support for performing operations using 8-bit floating point operands, such as BF8 operands.

Embodiments herein address the above-noted drawbacks by providing support for 8-bit floating point format operands in a computing architecture. In one implementation, the 8-bit floating point format discussed herein is the BF8 format. Embodiments introduce a variety of techniques for supporting for 8-bit floating point format operands in a computing architecture. One technique of embodiments is systolic dot product accumulate on 8-bit floating point format input operands. Another technique of embodiments is converting floating point data to or from 8-bit floating point format data. Another technique of embodiments is performing efficient stochastic rounding on floating point format data values. Another technique of embodiments is hybrid floating point systolic operations. A further technique of embodiments is performing mixed mode operations with 8-bit floating point format operands. The techniques of embodiments herein are described in further detail below.

Systolic Dot Product Accumulate on 8-Bit Floating Point Input Operands

Embodiments provide for systolic dot product accumulate on 8-bit floating point format input operands.

As previously discussed, conventional training platforms support IEEE-754 FP16 and BFLOAT16 data formats in high-performance systolic array implementations. These data formats are also supported in systolic dot-product accumulate (DPAS) engines. As noted above, deep neural networks can be trained using 8-bit floating point data format (BFLOAT8 or BF8, binary format=1s−5e−2m). BFLOAT8 can offer up to 2× improvement in training throughput compared to FP16 and BFLOAT16 implementations. However, there are no known conventional solutions that support systolic dot-product operations using the BFLOAT8 numeric format.

Embodiments provide extensions to the DPAS (dot product accumulate systolic) engine to support BF8 data format. Implementations provide instructions to perform matrix dot product on three input operands c+=a*b, where a and b matrices are of BF8 data type. In addition, embodiments provide hardware circuitry to fetch, decode and execute said instructions. In some implementations, the accumulated result of the dot product can be returned in either a 32-bit (FP32) or 16-bit (FP16, BF16) floating point. Embodiments provide the technical advantage of increasing systolic compute density and throughput, reducing data movement cost (as BF8 utilizes half the bandwidth and cache/register space compared to 16-bit data formats), and accelerating training by enabling mixed-precision BFLOAT8 training.

Embodiments provide a DPAS instruction to support dot-product and accumulate operations on input arguments presented in an 8-bit floating point (e.g., BF8) data format. FIG. 15 is a block diagram illustrating a BFLOAT8 (BF8) binary format 1500, in accordance with embodiments. The BF8 binary format 1500 is represented with sign 1510, exponent 1520, and mantissa 1530 bits. The sign bit 1510 is 1 bit, the exponent 1520 is 5 bits, and the mantissa 1530 is 2 bits. The 5-bit exponent 1520 uses an offset value of 15 that can represent normal floating point values between 6.1e−05 and 5.7344e+04. The BF8 binary format 1500 also supports subnormal values that extend the dynamic range down to the smallest representable value of 1.5e−05.

FIG. 16 is a block diagram illustrating a systolic DP 8-bit FP format operation 1610 performed by an instruction pipeline 1600, according to embodiments. The instruction pipeline 1600 can be configured to perform the systolic DP 8-bit format operation 1610, such as, but not limited to a dot product operation. The dot product of two vectors is a scalar value that is equal to sum of products of corresponding components of the vectors. The dot product can be calculated as shown in equation (1) below.

${\overset{\rightharpoonup}{a} \cdot \overset{\rightharpoonup}{b}} = {{\sum\limits_{i = 1}^{n}{a_{1}b_{1}}} = {{a_{1}b_{1}} + \cdots + {a_{n}b_{n}}}}$

The dot product can be used in a convolution operation for a neural network, such as a convolutional neural network (CNN). The instruction pipeline 1600 used to accelerate hardware instructions can include the instruction fetch and decode unit 1421, which can fetch and decode hardware instructions, and a controller unit 1620 (such as the scheduler controller 1422) that can schedule decoded instructions to one or more execution units within the compute blocks 1424A-1424N (collectively referred to as compute blocks 1424) and/or the matrix accelerator 1423. The instruction pipeline 1600 can also include a selection circuit 1630, such as a collection of multiplexors (muxes), to route input data to the compute blocks 1424 and/or the matrix accelerator 1423 in accordance with the 8-bit FP format encoded in the hardware instruction of the systolic DP 8-bit format operation 1610.

In one embodiment, a hardware instruction can be scheduled to the compute blocks 1424 and offloaded to the matrix accelerator 1423. The one or more hardware instructions and associated data to perform the systolic DP 8-bit FP format operation 1610 can be stored in the memory 1650. Output of the hardware instruction can also be stored in the memory 1650. The memory 1650 can be any of the memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430 as in FIG. 14. In some embodiments, memory 1650 can be one or more register files.

In one embodiment, the matrix accelerator 1423 can execute one or more hardware instructions to perform the systolic DP 8-bit format operation 1610 using systolic array circuit 1640. The systolic array circuit 1640 can include a combination of programmable and fixed function hardware that is configurable to perform dot product operations. While functional units within the compute blocks 1424 can also be configured to perform dot product operations, the systolic array circuit 1640 can be configured to perform a limited subset of dot product operations at a significantly higher throughput relative to the compute block 1424.

In embodiments herein, a DPAS instruction is provided to perform a systolic dot product and accumulate operation on 8-bit floating point format (such as BF8) source operands from a register file, accumulate the results at a chosen precision (fp32, fp16, bf16), and write back the final output to the register file. This DPAS instruction to perform the systolic DP 8-bit format operation 1610 accepts three input operands to compute c+=a*b, where ‘a’ and ‘b’ operands are of an 8-bit FP type, such as BF8. Some of the supported combinations of input and output operands are shown below.

dpas.<sdepth>x<rcount> <f32> <f32> <bf8> <bf8> dpas.<sdepth>x<rcount> <f16> <f16> <bf8> <bf8> dpas.<sdepth>x<rcount> <bf16> <bf16> <bf8> <bf8>  dst src0 src1 src2

DPAS is a multiply add and accumulate operation in a systolic pipeline with BFLOAT8 inputs (src1×src2). Each fused multiply-accumulate (FMA) stage of the systolic pipeline represents a 32-bit SIMD channel in the systolic array circuit 1640 and performs a DPAS operation on 4 input elements (e.g., dp4a operation) each from src1 and src2. The dst and src0 accept a IEEE754 float or half-float operands and src0 contains the accumulated output from the previous DPAS iterations in the systolic array. Embodiments can utilize any iteration of a block-normalize technique, including, but not limited to, dp4a, dp2a (block=2), dp8a (block=8), dp32a (block=32), and so on. Each block-normalize technique is associated with its own advantages (e.g., improved area efficiency) and disadvantages (e.g., loss of accuracy). The particular block-normalize technique implemented may be based on the particular application used.

The ‘sdepth’ parameter represents the systolic depth of the operation, which means a sequence of these ‘sdepth’ operations are performed advancing over successive registers. The output of each stage is maintained at 32-bit precision, which will be the accumulated input to the next systolic stage. The dst and src0 arguments can accept IEEE-754 float, half-float or bfloatl6 data types, the previously accumulated result is passed to the instruction via the source register (src0). The final accumulated output is converted to destination data format and written to the destination register (dst). The ‘rcount’ parameter is the repeat count of the operation, which means ‘rcount’ number of dpas instructions are generated with dst and src0 advancing successive registers, src1 remaining same and src2 advancing 32 elements.

In embodiments, the accumulator operand ‘c’ can be FP32, FP16 or BF16. The systolic array circuit 1640 hardware should support subnormal values on the input (i.e., DAZ=0). In embodiments, the input subnormal values can be upconverted and normalized on the grid before they are fed to a first stage of the systolic array circuit 1640.

In some implementations, a partial sum that is passed through input argument ‘c’ can be accumulated at the end of the systolic chain to minimize the precision loss due to the internal normalize and add operations. This accumulation of the accumulator input argument (‘c’) at the end of the systolic chain is referred to as “late accumulate”. The internal sum at each stage of the systolic array is accumulated and rounded into an FP32 value using round to nearest. In some embodiments, the accumulation of the accumulator input argument (‘c) can occur at a first stage of the systolic chain or can occur at any intermediate stage(s) of the systolic chain.

FIG. 17A is a block diagram illustrating a systolic array circuit 1700 to perform systolic dot product accumulate on 8-bit floating point format input operands, in accordance with embodiments. In one embodiment, the systolic dot product accumulate on 8-bit floating point format input operands depicted in FIG. 17A is an example dp4a operation. In one implementations, systolic array circuit 1700 is the same as systolic array circuit 1640 described with respect to FIG. 16. The systolic array circuit 1700 can include a combination of programmable and fixed function hardware that is configurable to perform dot product operations. Other variations and combinations of circuitry and elements of the systolic array circuit 1700 may be implemented and are not limited to those illustrated herein. FIG. 17A provides one example architecture of a systolic array circuit 1700, and other architectures may be implemented to provide the systolic dot product accumulate on 8-bit floating point format input operands operations as discussed herein.

Each FMA unit in the systolic array circuit 1700 performs a vector dot product operation (e.g., such as a 4-element vector dot product operation (dp4a)) on 4 pairs of BF8 input values from src1 and src2 registers. In one embodiment, each FMA unit includes a combination of multiplier 1710 a-1710 d and shifter 1715 b-1715 d pairs, as well as an adder 1720. A third input register src0 contains the partial accumulated sum from the previous dot-product iterations. Multiple such FMA units chained together in a systolic array can perform a DPAS operation as further discussed below. A systolic array implementation can chain these individual FMA units in any order possible that makes for an efficient design, the order of accumulation is not a concern.

In embodiments herein, the systolic array circuit 1700 should support subnormal values on BF8 inputs (e.g., DAZ=0). This may be accomplished by extending the input exponent and normalizing the subnormal input values on the grid. Multiplication can be performed using, for example, 4-bit multipliers 1710 a-1710 d and 1730 a-1730 d, without loss of precision. The outputs of the multipliers 1710 a-1710 d and 1730 a-1730 d can be normalized using shifters, such as 32-bit shifters 1715 a-1715 e and 1735 a-1735 e after each multiplier. Although the shifters 1715 a-1715 e, 1735 a-1735 e are depicted as 32-bit shifters, in embodiments herein the shifters 1715 a-1715 e, 1735 a-1735 e can be any arbitrary precision. For example, in cases where a block-normalize operation with large block size 32 is utilized, the shifters 1715 a-1715 e, 1735 a-1735 e can grow up to 48 bits. As such, although 32-bit shifters 1715 a-1715 e, 1735 a-1735 e are shown for illustrative purposes, embodiments are not limited to the specific 32-bit shifter size and the shifters 1715 a-1715 e, 1735 a-1735 e may be any arbitrary precision.

The normalized products output from the shifters 1715 a-1715 e, 1735 a-1735 e are added together in an adder, such as 5-way FP32 adder 1720, 1740, and rounded using round to nearest to produce an FP32 output. In some embodiments, the 5-way FP32 adder may be an N-way adder tree (where N is configurable) based on the block size selected for the normalization. In embodiments, any subnormal values on the FP32 intermediate results (e.g., at adders 1720, 1740) after each are flushed to zero.

As previously discussed, the systolic array circuit 1700 can implement late accumulation. For late accumulation, the src0 is accumulated at the end of the systolic chain at a final adder, such as FP32 adder 1750. As such, the ‘c’ value for the first stage (e.g., ‘depth 0’) of the systolic array circuit 1700 is zero. Late accumulation prevents loss of numeric accuracy of the accumulated output and can provide improved performed in workload level accuracy. As previously discussed, in some embodiments, the accumulation of the accumulator input argument (‘c) can occur at a first stage of the systolic chain or can occur at any intermediate stage(s) of the systolic chain.

The final output (e.g., dest (FP32) 1752) after late accumulation is rounded by the adder 1750 to the destination precision using round to nearest even (RNE). Implementations of the systolic array circuit 1700 can support multiple output formats, including FP32, FP16 and BF16, to name a few examples. In some embodiments, the subnormal values on the final output of adder 1750 are flushed to zero if the output is FP32 or BF16. In some embodiments, subnormal values are supported on FP16 outputs.

FIG. 17B is a block diagram illustrating a systolic array circuit 1755 to perform systolic dot product accumulate on 8-bit floating point format input operands, in accordance with embodiments. In one embodiment, the systolic dot product accumulate on 8-bit floating point format input operands depicted in FIG. 17B is an example dp2a operation, which is a 2-element vector dot product operation. In one implementations, systolic array circuit 1755 is the same as systolic array circuit 1640 described with respect to FIG. 16. The systolic array circuit 1755 can include a combination of programmable and fixed function hardware that is configurable to perform dot product operations. Other variations and combinations of circuitry and elements of the systolic array circuit 1755 may be implemented and are not limited to those illustrated herein. FIG. 17B provides one example architecture of a systolic array circuit 1755, and other architectures may be implemented to provide the systolic dot product accumulate on 8-bit floating point format input operands operations as discussed herein.

Each FMA unit in the systolic array circuit 1755 performs a vector dot product operation (e.g., such as a 2-element vector dot product operation (dp2a)) on 4 pairs of BF8 input values from src1 and src2 registers. In one embodiment, each FMA unit includes a combination of re-bias and normalize circuit 1760 a-1760 h, multiplier 1770 a-1770 d, and adders 1780 a-b, 1785 a-b. A third input register src0 contains the partial accumulated sum from the previous dot-product iterations. Multiple such FMA units chained together in a systolic array can perform a DPAS operation as further discussed below. A systolic array implementation can chain these individual FMA units in any order possible that makes for an efficient design, the order of accumulation is not a concern.

In embodiments herein, the systolic array circuit 1755 should support subnormal values on BF8 inputs (e.g., DAZ=0). This may be accomplished by extending the input exponent and normalizing the subnormal input values on the grid. Re-bias and normalize circuits 18760 a-1760 h can convert both the incoming operands (src1 (BF8) and src2 (BF8)) to a common binary format (e.g., FP32) that can accommodate both the 8-bit FP format and its subnormal values (e.g., DAZ=0).

Multiplication can be performed using, for example, FP32 multipliers 1770 a-1770 d, without loss of precision. The outputs of the multipliers 1710 a-1710 d can be added together in an adder tree (e.g., N-way adder tree based on selected block size), such as the adder tree provided by FP32 adder 1780 a, 1780 b and FP32 adder 1785 a, 1785 b, and rounded using round to nearest (RNE) to produce an FP32 output. In embodiments, any subnormal values on the FP32 intermediate results (e.g., at adders 1780 a-b, 1785 a-b) after each are flushed to zero.

As previously discussed, the systolic array circuit 1755 can implement late accumulation. For late accumulation, the src0 is accumulated at the end of the systolic chain at a final adder tree, such as provided by FP32 adder 1790, 1795. As such, the ‘c’ value for the first stage (e.g., ‘depth 0’) of the systolic array circuit 1755 is zero. Late accumulation prevents loss of numeric accuracy of the accumulated output and can provide improved performed in workload level accuracy. As previously discussed, in some embodiments, the accumulation of the accumulator input argument (‘c) can occur at a first stage of the systolic chain or can occur at any intermediate stage(s) of the systolic chain.

The final output (e.g., dest (FP32) 1792) after late accumulation is rounded by the adder 1795 to the destination precision using round to nearest even (RNE). Implementations of the systolic array circuit 1755 can support multiple output formats, including FP32, FP16 and BF16, to name a few examples. In embodiments, the subnormal values on the final output of adder 1795 are flushed to zero if the output is FP32 or BF16. In some embodiments, subnormal values are supported on FP16 outputs.

The following is an example pseudo code to implement systolic dot product accumulate on 8-bit floating point format input operands (such as BF8 operands), in accordance with embodiments.

if (Input is sNaN){  output Quietized_NaN(input); } else if (Input is qNaN){  output destination qNaN } else if (Input is Inf){  output destination Inf } else {   Step 1: Upconvert inputs, normalize subnormals.   Step 2: dpas( );   Step 3: Convert FP32 value to destination format, round to RNE.   Step 4: Flush output subnormals to zero } dpas( ) { // x[i], y[i] are the 8bits from Src1 and Src2 registers and Acc is the 32bits float // CLOCK 0: For the first module ACC = 0 Temp1 = RNE (x0[0] * y0[0] + x0[1] * y0[1]); Temp2 = RNE (x0[2] * y0[2] + x0[3] * y0[3]); ACC = RNE (Temp1 + Temp2); // CLOCK 1 : ACC from the previous stage is added here Temp1 = RNE (ACC + x1[0] * y[0] + x1[1] * y1[1]); Temp2 = RNE (x1[2] * y1[2] + x1[3] * y1[3]); ACC = RNE (Temp1 + Temp2); ... // After sdepth multiply accumulate operations // Late accumulate, input Src0 is added at the end Dst = RNE (Src0 + ACC); }

FIG. 18A illustrates a dot product with accumulate instruction 1800 executable by a systolic array circuit, according to embodiments described herein. FIG. 18A illustrates fields of a dot product with accumulation instruction operating on 8-bit floating point format input operands and executable by systolic matrix logic provided by an embodiment. FIG. 18A illustrates fields of a dot product with accumulate instruction 1800, which, when executed, causes a systolic matrix accelerator to execute a dot product with accumulate on 8-bit floating point format input operands (e.g., BF8 operands). In one embodiment, the instruction 1800 includes an opcode field 1802, a systolic depth 1804 (sdepth), a repeat count 1806 (rcount), and operand fields to specify a destination 1808, zeroth source 1810 (src0), first source 1812 (src1), and second source 1814 (src2).

The opcode field 1802 can specify an opcode that identifies the instruction 1800 to execution logic. In one embodiment the opcode field 1802 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a matrix accelerator (e.g., matrix accelerator 1423). In one embodiment, the opcode field 1802 can also include one or more bits that specify that the instruction 1800 is to be executed by special purpose dot product logic, such as dot product logic (e.g., systolic array circuit 1640) within a matrix accelerator 1423.

The systolic depth 1804 (sdepth) can be used to specify the number systolic layers to use to process the input data. In one embodiment the systolic depth 1804 can be provided as an immediate value. The repeat count 1806 (rcount) can be used to specify the number of dpas instructions that are generated with dst and src0 advancing successive registers, src1 remaining same, and src2 advancing N elements (where N is the destination format).

The destination 1808, zeroth source 1810 (src0), first source 1812 (src1), and second source 1814 (src2) can be used to specify a destination to which a calculation is written and a location from which source data can be retrieved. In one embodiment the destination 1808 can specify a register to which data is to be written. In one embodiment the destination 1808 can be a scalar register, although in some embodiments the destination can also be a vector register that stores output from multiple channels. The zeroth source 1810, first source 1812, and second source 1814 can be register or immediate values that include one or more channels of source data, each channel having four elements to be processed by the systolic array circuit.

In some embodiments, additional fields other than those illustrated may be present. For example, in one embodiment a source modifier field is present which specifies the numeric modification of a source operand. The value of each data element of a source operand can optionally have its absolute value taken and/or its sign inverted prior to delivery to the execution pipeline. The absolute value modifier can be applied prior to the negate modifier, such that a guaranteed negative value can be produced. In one embodiment, a saturation field is present, which can be used to control destination saturation. When saturation is enabled, output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data that is outside the saturation target range for the data type to the closest represented value with the target range.

FIG. 18B illustrates a program code compilation process 1815, according to an embodiment. In one embodiment, a source code level description 1820 of a software program is compiled at a compiler 1830, which can include multiple levels of compilations, to a level having an operation 1840 that includes or specifies an 8-bit dot product to be performed by processing logic. The operation 1840 can be an operation specified in an intermediate language or can be program code that references a primitive of a compute framework, such as a primitive provided by a machine learning framework. The operation 1840 that includes or specifies an 8-bit dot product may then be further compiled by an additional compiler 1850, which can be a shader compiler, into machine level object code 1860 that includes an 8-bit dot product instruction to be performed by an accelerator for matrix operations, as described herein.

FIG. 19 is a flow diagram illustrating an embodiment of a method 1900 for executing an instruction for systolic dot product accumulate on 8-bit floating point format input operands. Method 1900 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 1900 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-18 may not be repeated or discussed hereafter. In one implementation, a data processing system, such as data processing system 1400 of FIG. 14, may perform method 1900.

Method 1900 begins at processing block 1910 where a single instruction may be fetched and decoded to be executed within a GPGPU. In one implementation, the single instruction is decoded into a decoded matrix instruction that can operate on 8-bit floating point format operands to cause the GPGPU to perform a parallel dot product operation. At processing block 1920, a set of pipeline commands is determined to execute the decoded matrix instruction on a matrix accelerator using one or more 8-bit floating point format operands (such as BF8 operands).

Subsequently, at processing block 1930, the set of pipeline commands is scheduled to a systolic dot product pipeline to execute the decoded matrix instruction using the one or more 8-bit floating point format operands. Lastly, at processing block 1940, the decoded matrix instruction is retired in response to completion of the set of pipeline commands.

FIG. 20 is a flow diagram illustrating an embodiment of a method 2000 for systolic dot product accumulate on 8-bit floating point format input operands. Method 2000 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 2000 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-19 may not be repeated or discussed hereafter. In one implementation, a systolic array, such as systolic array circuit 1640 of FIG. 16 or systolic array circuit 1700 of FIG. 17, may perform method 2000.

Method 2000 begins at processing block 2010 where source values and a calculation depth for an instruction are fetched to be executed by a matrix operation accelerator of a GPGPU. In one implementation, the source values are 8-bit floating point format operands (such as BF8 operands). At processing block 2020, a set of products is generated based on an element-wise multiply of the source input elements using 4-bit multipliers.

At processing block 2030, multiplier outputs are normalized using 32-bit shifters for each multiplier. Then, at processing block 2040, a sum is calculated of the set of normalized multiplier outputs and the sum is rounded to nearest even. Lastly, at processing block 2050, at last depth layer of the matrix operation accelerator, a sum is calculated of the set of normalized multiplier outputs and an initial accumulator value. The sum is then rounded to a destination output precision using round to nearest even.

Converting Floating Point Data to or from 8-Bit Floating Point Format

Embodiments herein provide for converting floating point data to or from 8-bit floating point format data.

As previously discussed, advances in deep leaning have enabled ML models to take advantage of low-precision arithmetic for training neural networks. Conventional training platforms support IEEE-754 FP16 and BFLOAT16 data formats in high-performance systolic array implementations. These implementations use high-precision accumulators to prevent loss of accuracy during long chains of dot product computations. Within a neural network, these high precision outputs should be rounded down to low precision format during post-processing of a layer, before they can be sent to the next layer as inputs. For example, conventional hardware implementations for neural networks supports rounding from FP32 to FP16 and BF16.

As noted above, 8-bit FP format data (such as BFLOAT8, 1s-5e−2m) is the can improve training and inference performance. A hardware implementation of a BFLOAT8 FMA could use either an FP32 or an FP16 accumulator to preserve numeric accuracy. However, conventional systems do not have hardware support for rounding the FP32 or FP16 FMA output to BFLOAT8 during post processing. Conventional systems may provide a slower software implementation that uses sequence arithmetic and bitwise instructions to perform this rounding operation. For example, this functionality can be emulated in the software using a sequence of arithmetic, bitwise and compare instructions. This slower software implementation results in performance penalties for smaller and irregular kernels, which are often used in deep neural network training.

Embodiments propose an instruction to convert floating point data to 8-bit floating point format data. In one implementation, the conversion instruction of embodiments performs down conversion from IEEE-754 FP32 and FP16 to BFLOAT8 with nearest-to-even rounding. In one implementation, the conversion instruction of embodiments performs up-conversion from BFLOAT8 to FP32 and FP16 to facilitate mixed-precision compute operations with BFLOAT8 memory format.

Embodiments provide an instruction and hardware solution for convert floating point data to 8-bit floating point format data. The instruction and hardware techniques of embodiments herein replace a long sequence of instructions with a single instruction that can used by a programmer. This can result in performance improvements for irregular kernel operations in a neural network. Embodiments also enable mixed precision 8-bit floating point format (e.g., BFLOAT8) training that can accelerate training throughput of the neural network.

FIG. 21 is a block diagram illustrating an 8-bit FP format conversion operation 2110 performed by an instruction pipeline 2100, according to embodiments. The instruction pipeline 2100 can be configured to perform the 8-bit FP format conversion operation 2110. The instruction pipeline 2100 can be used to accelerate hardware instructions can include the instruction fetch and decode unit 1421, which can fetch and decode hardware instructions, and a controller unit 2120 (such as the scheduler controller 1422) that can schedule decoded instructions to one or more execution units within the compute blocks 1424A-1424N (collectively referred to as compute blocks 1424) and/or the matrix accelerator 1423. The instruction pipeline 2100 can also include a selection circuit 2130, such as a collection of multiplexors (muxes), to route input data to the compute blocks 1424 and/or the matrix accelerator 1423 in accordance with the 8-bit FP format encoded in the hardware instruction of the 8-bit FP format conversion operation 2110.

In one embodiment, a hardware instruction can be scheduled to the compute blocks 1424 and/or offloaded to the matrix accelerator 1423 (e.g., for computation using systolic array circuit 2140). The one or more hardware instructions and associated data to perform the 8-bit FP format conversion operation 2110 can be stored in the memory 2150. Output of the hardware instruction can also be stored in the memory 2150. The memory 2150 can be any of the memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430 as in FIG. 14.

In one embodiment, the compute blocks 1424 can execute one or more hardware instructions to perform 8-bit FP format conversion operation 2110 using processing unit 2160. The processing unit 2160 can include a combination of programmable and fixed function hardware that is configurable to perform 8-bit FP format conversion operations. In some implementations, processing unit 2160 may be vector processing unit (VPU). In some implementations, processing unit 2160 may be a floating point unit (FPU). The processing unit 2160 may include a conversion circuit 2162, round-to nearest (RNE) rounding circuit 2164, and a special processing circuit 2166.

In embodiments, the hardware instructions to perform 8-bit FP format conversion operation 2110 provide data conversion between IEEE-754 FP32 or FP16 data and BFLOAT8 formats. The data conversion may include down conversion from FP32/FP16 to 8-bit FP format (e.g., BF8) or up conversion from 8-bit FP format (e.g., BF8) to FP32/FP16. FIG. 15 discussed above depicts an example BF8 binary format that can be utilized as the 8-bit FP format of embodiments. The BFLOAT8 binary format is represented as a sign, exponent and mantissa bits. The 5-bit exponent uses an offset value of 15 that can represent normal floating point values between 6.1e−05 and 5.7344e+04. The format also supports subnormal values that extend the dynamic range down to the smallest representable value of 1.5e−05.

When down converting from FP32 or FP16 to BF8, the values are rounded using a round-to-nearest-even (RTNE) process. Subnormal values are supported in both cases of conversion from FP32 or FP16. When upconverting from BF8 to either FP16 or FP32, the 8-bit FP format (BF8) exponent values are appropriately scaled and the mantissa is zero extended.

In embodiments, the conversion circuit 2162 can include programmable and fixed function hardware to perform the conversion process described above. The RNE rounding circuit 2164 can include programmable and fixed function hardware to perform the RNE rounding of the converted data. The special processing circuit 2166 can include programmable and fixed function hardware that addresses corner cases encountered when converting and/or rounding the data, such as underflow, overflow, or de-normals, for example.

In some implementations, the instruction for conversion of 8-bit FP format data as described herein may take the following form:

mov dst, src0

When the conversion circuit 2162 is down converting from FP32/FP16 to BF8, the instruction should retain subnormal values on the output. In some embodiments, the special processing circuit 2166 may provide for saturation behavior that results in overflow (i.e., large values are not saturated to BF8_MAX). The RNE rounding circuit 2164 should round the mantissa using round-to-nearest-even process. Some example implementations of the instruction for conversion of 8-bit FP format data when performing down conversion from FP32 or FP16 to BF8 are as detailed as follows:

mov <bf8>, <fp32>

mov <bf8>, <fp16>

When the conversion circuit 2162 is up converting from FP32/FP16 to BF8, the exponent values are rescaled and the values re-normalized. The mantissa bits are extended with zeros on the LSB bits. Some example implementations of the instruction for conversion of 8-bit FP format data when performing up conversion from BF8 to FP32 or FP16 are as detailed as follows:

mov <fp32>, <bf8>

mov <fp16>, <bf8>

FIG. 22A illustrates an instruction 2200 executable by a processing unit, according to embodiments described herein. FIG. 22A illustrates fields of a mov instruction to convert 8-bit floating point format input operand and executable by a processing unit, such as a VPU or FPU, provided by an embodiment. FIG. 22A illustrates fields of a mov instruction 2200, which, when executed, causes a processing unit to execute a mov instruction to convert to or from an 8-bit floating point format input operands (e.g., BF8 operand). The mov instruction copies the data item referred to by its second operand (i.e. register contents, memory contents, or a constant value) into the location referred to by its first operand (i.e. a register or memory).

In one embodiment, the instruction 2200 includes an opcode field 2202 and operand fields to specify a destination 2204 and a source 2206 (src).

The opcode field 2202 can specify an opcode that identifies the instruction 2200 to execution logic. In one embodiment the opcode field 2202 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a processing unit of a compute block (e.g., compute block 1424).

The destination 2204 and source 2206 (src) can be used to specify a destination to which a calculation is written and a location from which source data can be retrieved. In one embodiment the destination 2204 can specify a register to which data is to be written. In one embodiment the destination 2204 can be a scalar register, although in some embodiments the destination can also be a vector register that stores output from multiple channels. The source (src) 2206 can be register or immediate values that include one or more channels of source data.

In some embodiments, additional fields other than those illustrated may be present. For example, in one embodiment a source modifier field is present which specifies the numeric modification of a source operand. The value of each data element of a source operand can optionally have its absolute value taken and/or its sign inverted prior to delivery to the execution pipeline. The absolute value modifier can be applied prior to the negate modifier, such that a guaranteed negative value can be produced. In one embodiment, a saturation field is present, which can be used to control destination saturation. When saturation is enabled, output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data that is outside the saturation target range for the data type to the closest represented value with the target range.

FIG. 22B illustrates a program code compilation process 2215, according to an embodiment. In one embodiment, a source code level description 2220 of a software program is compiled at a compiler 2230, which can include multiple levels of compilations, to a level having an operation 2240 that includes or specifies an 8-bit FP format conversion instruction to be performed by processing logic. The operation 2240 can be an operation specified in an intermediate language or can be program code that references a primitive of a compute framework, such as a primitive provided by a machine learning framework. The operation 2240 that includes or specifies an 8-bit FP format conversion instruction may then be further compiled by an additional compiler 2250, which can be a shader compiler, into machine level object code 2260 that includes an 8-bit FP format conversion instruction to be performed by a processing unit (e.g., VPU, FPU) of a compute block, as described herein.

The following is an example pseudo code to implement converting floating point data to or from 8-bit floating point format data (such as BF8 operands), in accordance with embodiments.

float src; bf8 dst; If (src == NaN) return Quieted_NaN; If (src == Inf) return Inf; If (src == 0.0) return 0.0; src_sm = convert_to_sign_magnitude_format(src); src_sm = apply_IEEE754_RNE (src_sm); If (src_sm > dest_max_val) /* saturation */  dst = inf If (src_sm < dest_min_val) /* dest_min_val smallest BF8 subnormal */  dst = 0.0 return dst

FIG. 23 is a flow diagram illustrating an embodiment of a method 2300 for executing an instruction for converting floating point data to 8-bit floating point format data. Method 2300 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 2300 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-22 may not be repeated or discussed hereafter. In one implementation, a data processing system, such as data processing system 1400 of FIG. 14, may perform method 2300.

Method 2300 begins at processing block 2310 where a single instruction is fetched and decoded to be executed within the GPGPU. In one implementation, the single instruction is decoded into a decoded instruction to cause the GPGPU to perform conversion of an operand to/from 8-bit floating point format. At processing block 2320, a set of commands is determined to execute the decoded vector instruction on a compute block of the GPGPU.

At processing block 2330, the set of commands is scheduled to a compute block of the GPGPU to execute the decoded instruction to perform conversion of an operand to/from 8-bit floating point format. Then, at processing block 2340, the decoded instruction is retired in response to completion of the set of commands.

FIG. 24 is a flow diagram illustrating an embodiment of a method 2400 for converting floating point data to 8-bit floating point format data. Method 2400 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 2400 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-23 may not be repeated or discussed hereafter. In one implementation, a processing unit, such as processing unit 2160 of FIG. 21, may perform method 2400.

Method 2400 begins at processing block 2410 where source value for an instruction is fetched to be executed by a compute block of a GPGPU. In one implementation, the source value is to be converted to a different data format and the source value is at least one of an 8-bit floating point format operand or is to be converted to an 8-bit floating point format operand. At decision block 2420, it is determined whether the source value is equal to 0, infinity, or not-a-number (NaN). If so, then method 2400 proceeds to processing block 2425, where the source value is returned to the destination as special use case value (e.g., 0, infinity, etc.).

If, at decision block 2420, the source value is not equal to 0, infinity, or NaN, the method 2400 proceeds to processing block 2430 where the source value is converted to sign magnitude format of destination by rescaling, normalizing and converting the source value. Then, at processing block 2440, a round to nearest even process is applied to the converted source value.

At decision block 2450, it is determined whether an overflow, underflow, or de-normal conditions has occurred. If so, the method 2400 proceeds to processing block 2460 where the converted and rounded source value is returned as a special use case value (e.g., 0, infinity, etc.). On the other hand, if an overflow, underflow, or de-normal condition has not occurred, then method 2400 proceeds to processing block 2470, where the converted and rounded source value is returned as the destination value.

Performing Efficient Stochastic Rounding on Floating Point Format Data Values

Embodiments provide for performing efficient stochastic rounding on floating point format data values.

As deep learning training is moving to 8-bit floating point format (e.g., BF8, 1s-5e-2m), the numeric errors introduced due to loss of precision can have significant impact on the ML model convergence. One of the ways to compensate for precision loss is to use ‘rounding’ when converting FP32 or FP16 accumulated FMA output to BF8 before it is passed to the next layer of the neural network as input.

However, rounding errors accumulated over long chains of dot product operations are also a concern to the numeric stability of iterative solvers used in deep neural network training. This problem is exacerbated at lower precision because the machine epsilon ‘ε’ (=0.125) is bigger for BF8 compared to FP16 (=4.88e−04) and BF16 (=3.90e−03).

When using BF8 data format across multiple workloads, stochastic rounding can reduce accumulation of rounding errors and assist in achieving convergence. Stochastic rounding refers to a rounding process that is non-deterministic and that rounds a real number to the next larger or smaller floating-point number with probabilities 1 minus the relative distances to those numbers. A full-fledged hardware support for stochastic rounding would include a floating-point pseudo random number generator that is expensive to build and validate.

However, in the context of deep neural network learning, deep learning training has fewer constraints on the random number generator and can reuse random numbers often without an impact to the numeric stability of the solvers. Based on the reduced random number generator constraints, embodiments provide for a combination of hardware and instructions to accelerate stochastic rounding using low-precision random bits (e.g., 8-bits for FP16→BF8 and 16-bits for FP32→FP16) generated and managed in software.

Embodiments herein provide one or more instructions to apply a stochastic rounding operation when a higher precision output of an arithmetic operation is converted to a lower-precision format (e.g., BF8 (1s−5e−2m), HF8 (1s4e3m), FP16 and BF16 floating point formats). These instructions may include one or two source operands of higher precision and a third input operand including integer random numbers generated by a pseudo random number generator (PRNG) that is software-based. In some implementations, the PRNG software may use an inexpensive PSNR algorithm, such as xoroshiro128++ or equivalent. The output is stored in the destination data format specified in the instruction.

The instructions and hardware of embodiments herein provide the technical advantage of replacing an extensive sequence of instructions with a single instruction that can used by a programmer for improved speed and efficiency of performance of the neural network training. Embodiments also decouple the PRNG from the rounding operation to reduce the complexity of the hardware, while allowing programmers to use algorithms for generating and managing (caching and reuse) random numbers. Furthermore, embodiments accelerate the back-propagation of BFLOAT8 mixed precision training for improved speed and efficiency of the neural network training.

FIG. 25 is a block diagram illustrating an 8-bit FP format conversion with stochastic rounding operation 2510 performed by an instruction pipeline 2500, according to embodiments. The instruction pipeline 2500 can be configured to perform the 8-bit FP format conversion with stochastic rounding operation 2510. The instruction pipeline 2500 can be used to accelerate hardware instructions can include the instruction fetch and decode unit 1421, which can fetch and decode hardware instructions, and a controller unit 2520 (such as the scheduler controller 1422) that can schedule decoded instructions to one or more execution units within the compute blocks 1424A-1424N (collectively referred to as compute blocks 1424) and/or the matrix accelerator 1423. The instruction pipeline 2500 can also include a selection circuit 2530, such as a collection of multiplexors (muxes), to route input data to the compute blocks 1424 and/or the matrix accelerator 1423 in accordance with the 8-bit FP format encoded in the hardware instruction of the 8-bit FP format conversion with stochastic rounding operation 2510.

In one embodiment, a hardware instruction can be scheduled to the compute blocks 1424 and/or offloaded to the matrix accelerator 1423 (e.g., for computation using systolic array circuit 2540). The one or more hardware instructions and associated data to perform the 8-bit FP format conversion with stochastic rounding operation 2510 can be stored in the memory 2550. Output of the hardware instruction can also be stored in the memory 2550. The memory 2550 can be any of the memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430 as in FIG. 14.

In one embodiment, the compute blocks 1424 can execute one or more hardware instructions to perform 8-bit FP format conversion with stochastic rounding operation 2510 using processing unit 2560. The processing unit 2560 can include a combination of programmable and fixed function hardware that is configurable to perform 8-bit FP format conversion with stochastic rounding operations. In some implementations, processing unit 2560 may be vector processing unit (VPU). In some implementations, processing unit 2560 may be a floating point unit (FPU). The processing unit 2560 may include a conversion circuit 2562, stochastic rounding circuit 2564, and a special processing circuit 2566.

In embodiments, the instruction to perform 8-bit FP format conversion with stochastic rounding operation can perform stochastic rounding during conversion from a higher precision floating point to a lower precision floating point. The instruction can take the following format:

srnd dest, src0, src1

In the instruction, the src0 is the source operand that contains the high-precision floating point input and src1 contains a random integer used by the rounding hardware. The random integer is generated by software using a PRNG algorithm, such as xoroshiro128++. The output of the rounding operation is returned in dst in the low precision floating point format specified by the instruction opcode.

During the conversion performed by conversion circuit 2562, a normalized sign-magnitude representation of src0 is generated. The conversion circuit 2562 can include programmable and fixed function hardware to perform the conversion process. Then, the stochastic rounding circuit 2564 utilizes a fixed-point adder 2565 to add a random integer from src1 to the normalized sign-magnitude representation of src0 to generate an intermediate result. The random integer is a PRNG 2570 generated by software using a PRNG algorithm. The stochastic rounding circuit 2564 then truncates the intermediate result to a size of the destination mantissa format after performing any exponent adjustment. The stochastic rounding circuit 2564 can include programmable and fixed function hardware to perform the stochastic rounding process. The special processing circuit 2566 can include programmable and fixed function hardware that addresses corner cases encountered when converting and/or rounding the data, such as underflow, overflow, or de-normals, for example.

In some embodiments, the number of random bits used for the rounding operation can depend on the input and output data formats defined in the instruction opcode. The following Table 1 provides a list of example supported input and output formats and the number random bits utilized to perform the rounding operation.

TABLE 1 random bits Src0 Dest N K (N − K) Instruction syntax FP32 BF8 23 2 21 (src1[20:0]) srnd rZ:bf8 rX:f rY:dw FP16 BF8 10 2 8 (src1[7:0]) srnd rZ:bf8 rX:hf rY:w BF16 BF8 7 2 5 (src1[4:0]) srnd rZ:bf8 rX:bf16 rY:w FP32 FP16 23 10 13 (src1[12:0]) srnd rZ:hf rX:f rY:dw FP32 BF16 23 7 16 (src1[15:0]) srnd rZ:bf16 rX:f rY:dw

In some embodiments, the width of the random number can vary depending on source and destination data format. Assuming source data format has N-bits of mantissa and destination data format has K-bits of mantissa, then (N-K) bits random numbers can be used to perform the rounding at the stochastic rounding circuit 2564.

FIG. 26 is a block diagram illustrating fixed-point addition 2600 of sign-magnitude representation of the mantissa and the random number, in accordance with embodiments. A source mantissa 2601 (with leading 1) and a random number 2605 are depicted as being added to generate an addition result 2610. The source mantissa include N bits 2602 of mantissa, with K-bits 2604 of the mantissa representing the number of mantissa bits used in the destination format. Before addition, the bits of random number 2605 are aligned to (N-K) least significant bits of source mantissa 2601. The addition result 2610 depicts the results of the addition, where there are two leading bits (X) and the remaining addition of mantissa bits (x).

FIG. 27A illustrates an instruction 2700 executable by a processing unit, according to embodiments described herein. FIG. 27A illustrates fields of an instruction to convert a floating point format input operand using stochastic rounding. The instruction is executable by a processing unit, such as a VPU or FPU, provided by an embodiment. FIG. 27A illustrates fields of an instruction 2700, which, when executed, causes a processing unit to execute an instruction to convert floating point format input operands using stochastic rounding. In one embodiment, the instruction 2700 includes an opcode field 2702 and operand fields to specify a destination 2704, zeroth source (src0) 2706, and a first source (src1) 2708.

The opcode field 2702 can specify an opcode that identifies the instruction 2700 to execution logic. In one embodiment the opcode field 2702 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a processing unit of a compute block (e.g., compute block 1424).

The destination 2704, zeroth source 2706 (src0), and first source 2708 (src1) can be used to specify a destination to which a calculation is written and a location from which source data can be retrieved. In one embodiment the destination 2704 can specify a register to which data is to be written. In one embodiment the destination 2704 can be a scalar register, although in some embodiments the destination can also be a vector register that stores output from multiple channels. The zeroth source (src0) 2706 and first source (src1) 2708 can be registers or immediate values that include one or more channels of source data.

In some embodiments, additional fields other than those illustrated may be present. For example, in one embodiment a source modifier field is present which specifies the numeric modification of a source operand. The value of each data element of a source operand can optionally have its absolute value taken and/or its sign inverted prior to delivery to the execution pipeline. The absolute value modifier can be applied prior to the negate modifier, such that a guaranteed negative value can be produced. In one embodiment, a saturation field is present, which can be used to control destination saturation. When saturation is enabled, output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data that is outside the saturation target range for the data type to the closest represented value with the target range.

FIG. 27B illustrates a program code compilation process 2715, according to an embodiment. In one embodiment, a source code level description 2720 of a software program is compiled at a compiler 2730, which can include multiple levels of compilations, to a level having an operation 2740 that includes or specifies an FP format conversion instruction using stochastic rounding to be performed by processing logic. The operation 2740 can be an operation specified in an intermediate language or can be program code that references a primitive of a compute framework, such as a primitive provided by a machine learning framework. The operation 2740 that includes or specifies an FP format conversion with stochastic rounding instruction may then be further compiled by an additional compiler 2750, which can be a shader compiler, into machine level object code 2760 that includes an FP format conversion with stochastic rounding instruction to be performed by a processing unit (e.g., VPU, FPU) of a compute block, as described herein.

The following is a first example of pseudo code to implement efficient stochastic rounding on floating point format data values, in accordance with embodiments.

f (Input is sNaN){ output Quieted_NaN(input) } else if (Input is qNaN){ output destination format qNaN } else if (Input is Inf){ output destination format Inf } else if (Input is Zero){ output destination format Zero } else { if (Input is denormal number){  Normalize the input mantissa to M = 1.XXX..XX format (N+1 bits)  out_exponent = input_exponent − mantissa_shift_bits } else{  Concatenate the leading 1 with input mantissa to M = 1.XXX..XX  (N+1 bits)  out_exponent = input_exponent }

-   -   Extract the desired random number R from Src1: R=Src1 [N-K-1:0]     -   Align LSB of R and M, and perform fixed point addition M+R to         get addition result A

if (A has carry over bit){  Right shift A by 1bit  out_exponent++ } if (out_exponent > DestMaxExponent) {   //overflow   Output the +/−FMAX based on the input sign   }   else if (out_exponent < DesMinNormalExponent)   {   //Output denormal number

-   -   Denormalized the addition result A with destination bounded         exponent.     -   Truncate A with destination mantissa precision     -   Assembly output with bounded exponent and truncated mantissa

  }   else   {   //Output normal number   Truncate addition result A with destination mantissa precision   Assembly output with exponent and truncated mantissa  } }

The following is a second, simplified example of pseudo code to implement efficient stochastic rounding on floating point format data values, in accordance with embodiments.

float src; bf8 dst; If (src == NaN) return Quieted_NaN; If (src == Inf) return Inf; If (src == 0.0) return 0.0; If (src == input_subnormal)  Normalize_A to 1.xxxxx format; src_sm = convert_to_sign_magnitude_format(A); src_sm += random_number; If (src_sm > dest_max_val)   dst = inf else   dst = round_to_zero(src_sm) return dst

FIG. 28 is a flow diagram illustrating an embodiment of a method 2800 for executing an instruction for performing efficient stochastic rounding on floating point values. Method 2800 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 2800 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-27 may not be repeated or discussed hereafter. In one implementation, a data processing system, such as data processing system 1400 of FIG. 14, may perform method 2800.

Method 2800 begins at processing block 2810 where a single instruction is fetched and decoded to be executed within the GPGPU. In one implementation, the single instruction decoded into a decoded instruction to cause the GPGPU to perform conversion of 8-bit floating point format with stochastic rounding. Then, at processing block 2820, a set of commands is determined to execute the decoded vector instruction on a compute block of the GPGPU.

At processing block 2830, the set of commands is scheduled to a compute block of the GPGPU to execute the decoded instruction to perform conversion of 8-bit floating point format with stochastic rounding. Lastly, at processing block 2840, the decoded instruction is retired in response to completion of the set of commands.

FIG. 29 is a flow diagram illustrating an embodiment of a method 2900 for performing efficient stochastic rounding on floating point values. Method 2900 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 2900 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-28 may not be repeated or discussed hereafter. In one implementation, a processing unit, such as processing unit 2560 of FIG. 25, may perform method 2900.

Method 2900 begins at processing block 2910 where a source value is fetched for an instruction to be executed by a compute block of a GPGPU. In one implementation, the source value is to be converted to from a higher precision floating point to a lower precision floating point. Then, at decision block 2920, it is determined whether the source value is equal to 0, infinity, or NaN. If so, then method 2900 proceeds to processing block 2925 where the source value is returned to the destination as special use case value. If, at decision block 2920, the source value is not equal to 0, infinity, or NaN, then method 2900 proceeds to processing block 2930 where the source value is converted to sign magnitude format of destination and the converted source value is normalized.

Subsequently, at processing block 2940, a random number is added to the converted and normalized source value. In one implementation, the random number has a size that is determined based on data format of source and destination operands. In one implementation, the random number is obtained from PRNG software. At processing block 2950, exponent adjustment of the resulting sum is performed and the resulting sum is truncated to a size of the destination operand mantissa format to generate a resulting destination value.

At decision block 2960, it is determined whether an overflow, underflow, or de-normal condition has occurred. If so, then method 2900 proceeds to processing block 2970 where a special use case value is returned as the resulting destination value. On the other hand, if an overflow, underflow, or de-normal condition has not occurred, then method 2900 proceeds to processing block 2980 where the resulting destination value is returned.

Hybrid Floating Point Systolic Operations

Embodiments herein provide for hybrid floating point systolic operations.

Algorithmic advances in deep leaning have enabled models to take advantage of the low precision arithmetic for training neural networks. The noise resilient properties of deep neural networks also have enabled experimentation with custom data formats that could be utilized for various deep learning tasks. One such custom data format that is widely accepted in the deep learning community and adapted by hardware manufacturers is BFLOAT16.

As smaller bit widths (8 bits and lower) are utilized in deep learning, further customization of data formats may be implemented for efficient allocation of bits. For example, it is known that during backpropagation error gradients that tend to have wider distributions utilize data formats with higher dynamic range (i.e., bigger exponent), while the forward (or inference) path can benefit from higher numeric precision (i.e., bigger mantissa) to reduce numeric errors. This behavior is more apparent in smaller models (fewer model parameters) that are optimized for edge devices. For smaller bit-width data formats this leads to a trade-off between dynamic range and numeric precision.

In addition to trading bit allocations between exponent and mantissa, floating point formats can also customize numeric distribution by selecting an appropriate exponent bias or zero-point of the numeric distribution. Given the typical Gaussian-like data distributions (around 0) of most tensors used in deep learning applications, an exponent bias to maximize the number of smaller values that can be represented by the format is typically selected. This can partly compensate for having a smaller dynamic range by prioritizing the relevant parts of the numeric distribution.

Two 8-bit floating point representations have been introduced that can be used for training deep neural networks. One of the formats, BFLOAT8, uses ‘s1.e5.m2’ binary representation with a symmetric distribution of numbers. The other format, HFLOAT8, is represented in ‘s1.e4.m3’ format with a non-symmetric exponent bias with number distribution skewed towards smaller numeric values. Using a combination of BFLOAT8 and HFLOAT8 formats together to address different parts of the training pipeline may produce improved model accuracy. The mixing of multiple data formats into a single training flow can result in hybrid floating point operations between input matrices represented in different binary formats. As the industry moves towards 8-bit and sub-8-bit data formats, these kinds of hybrid operations will become more prevalent. However, conventional systems having floating point hardware do not support arithmetic operations between operands that use different binary encoding or use non-conventional exponent bias.

Embodiments address this technical problem by providing extensions to DPAS hardware to support custom binary encoding for the input operands to enable the hybrid floating point operations. The binary format information of the input operands, such as exponent size and/or exponent bias, can be either built into the hardware or can be optionally expressed as part of instruction encoding. The hardware extensions of embodiments can utilize that information to re-bias and convert the input arguments to a common internal format before performing the requested arithmetic operation.

FIG. 30 is a block diagram illustrating two 8-bit floating point formats that use a different binary encoding and exponent bias, in accordance with embodiments. A BFLOAT8 (or Brain-Float8) format 3000 on the left shows BFLOAT8 binary format that uses s1.e5.m2 format. The s1.e5.m2 format include 1 sign bit 3002, 5 exponent bits 3004, and 2 mantissa bits 3006. A HFLOAT 8 (or Hybrid-Float8) format 3010 on the right shows HFLOAT8 binary format that uses s1.e4.m3 format. The s1.e4.m3 format include 1 sign bit 3012, 4 exponent bits 3014, and 3 mantissa bits 3016. In addition, the HFLOAT8 format 3010 uses a larger exponent bias to shift the number distribution towards smaller numeric values. The differences between these two formats are outlined in the Table 2 below.

TABLE 2 Binary Exponent Max Min Min Format Bias Normal Normal Subnormal BFLOAT8 1s, 5e, 2m 15 57344 6.10e−5 1.52e−5 HFLOAT8 1s, 4e, 3m 11 15 9.76e−4 1.22e−4

The hybrid floating hardware of embodiments herein provides technical advantages over the drawbacks discussed above by enabling applications to select from list of available floating point formats that are most suitable for different parts of the training pipeline to maximize accuracy. Furthermore, embodiments can support multiple data formats with incremental changes to the hardware. This improves processor performance and neural network training throughput.

FIG. 31 is a block diagram illustrating a hybrid 8-bit FP format systolic operation 3110 performed by an instruction pipeline 3100, according to embodiments. The instruction pipeline 3100 can be configured to perform the hybrid 8-bit FP format systolic operation 3110, such as, but not limited to a dot product operation. The dot product of two vectors is a scalar value that is equal to sum of products of corresponding components of the vectors. The dot product can be calculated as shown in equation (1) below.

${\overset{\rightharpoonup}{a} \cdot \overset{\rightharpoonup}{b}} = {{\sum\limits_{i = 1}^{n}{a_{1}b_{1}}} = {{a_{1}b_{1}} + \cdots + {a_{n}b_{n}}}}$

The dot product can be used in a convolution operation for a neural network, such as a convolutional neural network (CNN). The instruction pipeline 3100 used to accelerate hardware instructions can include the instruction fetch and decode unit 1421, which can fetch and decode hardware instructions, and a controller unit 3120 (such as the scheduler controller 1422) that can schedule decoded instructions to one or more execution units within the compute blocks 1424A-1424N (collectively referred to as compute blocks 1424) and/or the matrix accelerator 1423. The instruction pipeline 3100 can also include a selection circuit 3130, such as a collection of multiplexors (muxes), to route input data to the compute blocks 1424 and/or the matrix accelerator 1423 in accordance with the hybrid 8-bit FP formats encoded in the hardware instruction of the hybrid 8-bit FP format systolic operation 3110.

In one embodiment, a hardware instruction can be scheduled to the compute blocks 1424 and offloaded to the matrix accelerator 1423. The one or more hardware instructions and associated data to perform the hybrid 8-bit FP format systolic operation 3110 can be stored in the memory 3150. Output of the hardware instruction can also be stored in the memory 3150. The memory 3150 can be any of the memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430 as in FIG. 14.

In one embodiment, the matrix accelerator 1423 can execute one or more hardware instructions to perform the hybrid 8-bit FP format systolic operation 3110 using systolic array circuit 3140. The systolic array circuit 3140 can include a combination of programmable and fixed function hardware that is configurable to perform dot product operations. While functional units within the compute blocks 1424 can also be configured to perform dot product operations, the systolic array circuit 3140 can be configured to perform a limited subset of dot product operations at a significantly higher throughput relative to the compute block 1424.

In some embodiments, a DPAS instruction is provided to perform a systolic dot product and accumulate operation on hybrid 8-bit floating point format data (such as BF8 and HF8) source operands from a register file, accumulate the results at a chosen precision (fp32, fp16, bf16), and write back the final output to the register file. This DPAS instruction to perform the hybrid 8-bit FP format systolic operation 3110 accepts three input operands to compute c+=a*b, where ‘a’ and ‘b’ operands are of hybrid 8-bit FP types, such as BF8 and HF8. Other combinations and variations of FP format types of the input operands are possible in embodiments and are not limited to the BF8 and HF8 formats.

FIG. 32 is a block diagram illustrating a hybrid FMA unit 3200 of a systolic array circuit to perform hybrid floating point systolic operations, in accordance with embodiments. In one implementation, hybrid FMA unit 3200 may be part of systolic array circuit 3140 described with respect to FIG. 31. In one implementation, hybrid FMA unit 3200 performs operations of a DPAS instruction having hybrid FP format operands. A hybrid-FMA implementation of hybrid FMA unit 3200 can accept custom floating point formats and internally convert them to a higher precision common format before performing arithmetic operations.

In embodiments, the information regarding the custom binary format, such as number of bits assigned for exponent and the exponent offset to be used, can be passed along in the instruction as an integer bitmap (shown below as “imm”, “<imm.cbf>”) as the fourth argument to the FMA instruction. A few examples of the hybrid DPAS instruction of embodiments are shown below using various combinations of input (e.g., BF8 and HF8) and output arguments.

hdpas_01.<sdepth>x<rcount> <f32> <f32> <hf8> <bf8> <imm.cbf> hdpas_02.<sdepth>x<rcount> <f16> <fl6> <bf8> <hf8> <imm.cbf> hdpas_12.<sdepth>x<rcount> <f32> <f32> <hf8> <hf8> <imm.cbf>  dst src0 src1 src2. imm

The instruction encoding can be represented as <hdpas_xx>, where ‘xx’ indicates which of the input arguments (src1, src2, or both) are allowed to use the custom input format. Implementations of the instruction encoding can vary depending on the encoding scheme used by the target architecture.

With reference to FIG. 32, a hybrid-FMA operation of embodiments performed by hybrid FMA unit 3200 is performed on src1 and src2 operands that are expressed in HFLOAT8 and BFLOAT8 data formats, respectively. Both of these formats use not only different binary format with different bit allocations for exponent and mantissa, but they also use different exponent bias (e.g., BFLOAT8 bias=15, HFLOAT8 bias=11).

The hybrid FMA unit 3200 may include a plurality of re-bias and normalize units 3210 a-h, a plurality of multipliers 3220 a-d, a plurality of shifters 3230 a-3230 r, and an adder 3240. The details of internal bit widths may vary in the hybrid FMA unit 3200 depending on the of input and output precision requirements.

A first stage of the hybrid FMA unit 3200 includes the re-bias & normalize units 3210 a-3210 h. The re-bias and normalize units 3210 a-3210 h can convert both incoming operands (src1 (HF8) and src2 (BF8)) to a common ‘s1.e8.m3’ binary format that can accommodate both BFLOAT8 and HFLOAT8 formats and their subnormal values (e.g., DAZ=0).

A second stage of the hybrid FMA unit 3200 includes the multipliers 3220 a-3220 d. The multipliers 3220 a-3220 d use the extended s1.e8.m3 format as input and produce an intermediate 17 bit sign-magnitude representation (s1.e8.m2.6).

A third stage of the hybrid FMA unit 3200 includes the shifters 3230 a 3230 e. The shifters 3230 a-3230 e can normalize the multiplier 3220 a-3220 d outputs, along with src0 (which contains a previous accumulated sum) using, for example, 32-bit shifters.

A final stage of the hybrid FMA unit includes the adder 3240. The adder 3240 includes an adder tree that produces a 27-bit mantissa as part of, for example, an s1.e8.m2.27 format result. The adder 3240 rounds this result down to a s1.e8.23m format destination result using round to nearest even method.

FIG. 33A illustrates a hybrid dot product with accumulate instruction 3300 executable by a systolic array circuit, according to embodiments described herein. FIG. 33A illustrates fields of a hybrid dot product with accumulation instruction 3300 operating on hybrid 8-bit floating point format input operands and executable by systolic matrix logic provided by an embodiment. FIG. 33A illustrates fields of a hybrid dot product with accumulate instruction 3300, which, when executed, causes a systolic matrix accelerator to execute a dot product with accumulate on hybrid 8-bit floating point format input operands (e.g., BF8 and HF8 operands). In one embodiment, the instruction 3300 includes an opcode field 3302, a systolic depth 3304 (sdepth), a repeat count 3306 (rcount), operand fields to specify a destination 3308, zeroth source 3310 (src0), first source 3312 (src1), and second source 3314 (src2), and an integer bitmap (imm) field 3316.

The opcode field 3302 can specify an opcode that identifies the instruction 3300 to execution logic. In one embodiment the opcode field 3302 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a matrix accelerator (e.g., matrix accelerator 1423). In one embodiment, the opcode field 3302 can also include one or more bits that specify that the instruction 3300 is to be executed by special purpose dot product logic, such as dot product logic (e.g., systolic array circuit 3140) within a matrix accelerator 1423.

The systolic depth 3304 (sdepth) can be used to specify the number systolic layers to use to process the input data. In one embodiment the systolic depth 3304 can be provided as an immediate value. The repeat count 3306 (rcount) can be used to specify the number of dpas instructions that are generated with dst and src0 advancing successive registers, src1 remaining same, and src2 advancing N elements (where N is the destination format).

The destination 3308, zeroth source 3310 (src0), first source 3312 (src1), and second source 3314 (src2) can be used to specify a destination to which a calculation is written and a location from which source data can be retrieved. In one embodiment the destination 3308 can specify a register to which data is to be written. In one embodiment the destination 3308 can be a scalar register, although in some embodiments the destination can also be a vector register that stores output from multiple channels. The zeroth source 3310, first source 3312, and second source 3314 can be register or immediate values that include one or more channels of source data, each channel having four elements to be processed by the systolic array circuit.

The integer bitmap (imm) field 3316 can be used to specify information regarding the custom binary format of at least one of the source operands (e.g., src1 3312 and/or src2 3314), such as number of bits assigned for exponent and the exponent offset to be used. This information can be passed along in the instruction 3300 as an integer bitmap in the imm field 3316.

In some embodiments, additional fields other than those illustrated may be present. For example, in one embodiment a source modifier field is present which specifies the numeric modification of a source operand. The value of each data element of a source operand can optionally have its absolute value taken and/or its sign inverted prior to delivery to the execution pipeline. The absolute value modifier can be applied prior to the negate modifier, such that a guaranteed negative value can be produced. In one embodiment, a saturation field is present, which can be used to control destination saturation. When saturation is enabled, output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data that is outside the saturation target range for the data type to the closest represented value with the target range.

FIG. 33B illustrates a program code compilation process 3315, according to an embodiment. In one embodiment, a source code level description 3320 of a software program is compiled at a compiler 3330, which can include multiple levels of compilations, to a level having an operation 3340 that includes or specifies a hybrid 8-bit FP dot product to be performed by processing logic. The operation 3340 can be an operation specified in an intermediate language or can be program code that references a primitive of a compute framework, such as a primitive provided by a machine learning framework. The operation 3340 that includes or specifies a hybrid 8-bit FP dot product may then be further compiled by an additional compiler 3350, which can be a shader compiler, into machine level object code 3360 that includes a hybrid 8-bit FP dot product instruction to be performed by an accelerator for matrix operations, as described herein.

The following is an example of pseudo code to implement hybrid floating point systolic operations, in accordance with embodiments.

  exponent_bias_1, exponent_bias_2 = Instruction_decode(op_code)   // convert src1 & src2 to s1.e8.m3 format, support denormals  Temp1 = re_bias_normalize_src1(src1[0], exponent_bias1, denormals=True);  Temp2 = re_bias_normalize_src2(src2[0], exponent_bias1, denormals=True);   ...  Temp7 = re_bias_normalize_src1(src1[3], exponent_bias1, denormals=True);  Temp8 = re_bias_normalize_src2(src2[3], exponent_bias1, denormals=True); // Multiply  PROD0 = temp1 * temp2;   ...  PROD3 = temp7 * temp8; // Normalize, Add  ACC = NORM_ADD (src0 + PROD0 +.. + PROD3);  // Round with RNE to produce s1.e8.m23  dst = RNE(ACC);

FIG. 34 is a flow diagram illustrating an embodiment of a method 3400 for executing an instruction for hybrid floating point systolic operations. Method 3400 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 3400 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-33 may not be repeated or discussed hereafter. In one implementation, a data processing system, such as data processing system 1400 of FIG. 14, may perform method 3400.

Method 3400 begins at processing block 3410 where a single instruction is fetched and decoded to be executed within a GPGPU. In one implementation, the single instruction decoded into a decoded matrix instruction that can operate on hybrid 8-bit floating point format operands to cause the GPGPU to perform a parallel dot product operation. At processing block 3420, a set of pipeline commands is determined to execute the decoded matrix instruction on a matrix accelerator using one or more hybrid 8-bit floating point format operands.

Subsequently, at processing block 3430, the set of pipeline commands is scheduled to a systolic dot product pipeline to execute the decoded matrix instruction using the one or more hybrid 8-bit floating point format operands. Lastly, at processing block 3440, the decoded matrix instruction is retired in response to completion of the set of pipeline commands.

FIG. 35 is a flow diagram illustrating an embodiment of a method 3500 for hybrid floating point systolic operations. Method 3500 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 3500 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-34 may not be repeated or discussed hereafter. In one implementation, a systolic array, such as systolic array circuit 3140 of FIG. 31, may perform method 3500.

Method 3500 begins at processing block 3510 where source values and a calculation depth are fetched for an instruction to be executed by a matrix operation accelerator of a GPGPU. In one implementation, the source values are hybrid 8-bit floating point format operands. At processing block 3520, source value inputs are re-biased and normalized as part of converting to common binary format.

Subsequently, at processing block 3530, a set of products is generated based on an element-wise multiply of the source input elements in the common binary format. Then, at processing block 3540, the multiplier outputs and the accumulator input are normalized using shifters for each multiplier and for the accumulator input. At processing block 3550, a sum of the set of normalized multiplier outputs is calculated and the sum is rounded to nearest even. Lastly, at processing block 3560, the sum is rounded to a destination output precision using round to nearest even.

Performing Mixed Mode Operations with 8-Bit Floating Point Operands

Embodiments provide for performing mixed mode operations with 8-bit floating point format operands.

Algorithmic advances in deep leaning have enabled models to take advantage of the low precision arithmetic for training neural networks. Conventional training platforms can support IEEE-754 FP16 and BFLOAT16 data formats in high-performance systolic array implementations. However, 8-bit FP (such as BFLOAT8, 1s-5e-2m) may be utilized to boost training and inference performance.

While a large percentage of core compute operations of a neural network, such as Convolution and Linear layers may be able to utilize the 8-bit FP format data type, there is still a portion of deep neural networks that would operate under a mixed precision regime (e.g., 8-bit FP format and 16-bit or 32-bit FP format). Some examples of the portions of a deep neural network that would operate under a mixed precision regime are BatchNorm and LayerNorm operations, which would maintain their internal statistics (such as mean and variance) at a higher precision while the layer accepts 8-bit FP format inputs (e.g., BFLOAT8) coming from the previous layers.

The current approach of conventional systems to deal with this mixed precision problem is to upconvert the input tensor to suitable higher precision format before performing operations and later down convert to the lower precision for systolic or output tensor. However, these conversion operations of the conventional approaches incur additional overheads to store extra high precision copies of the input tensor and increase register bandwidth pressure and dependency.

Embodiments herein address these technical problems by providing instructions to perform mixed-mode operations on 8-bit FP format (e.g., BFLOAT8 and other IEEE-754 FP formats) input operands. FIG. 15 discussed above depicts an example BF8 binary format that can be utilized as the 8-bit FP format of embodiments. The BFLOAT8 binary format is represented as a sign, exponent and mantissa bits. The 5-bit exponent uses an offset value of 15 that can represent normal floating point values between 6.1e−05 and 5.7344e+04. The format also supports subnormal values that extend the dynamic range down to the smallest representable value of 1.5e−05.

These instructions to perform mixed mode operations can accept at least one input operand in 8-bit FP format (e.g., BFLOAT8) while other inputs can be standard float or half-float format, for example. Embodiments provide a set of instructions for frequently-occurring operations, such as multiply (MUL), ADD, multiply-accumulate (MAC), SEL, and subtraction (SUB), that can operate on the mixed-mode operands discussed above.

Embodiments herein provide technical advantages over the above-noted technical problems by reducing the footprint and bandwidth requirements to the register file. Furthermore, embodiments improve end-to-end training performance for networks that have a large percentage of, for example, BatchNorm and LayerNorm operations. In addition, enabling mixed precision 8-bit FP format training can help accelerate training in neural networks in terms of training throughput.

FIG. 36 is a block diagram illustrating a mixed mode 8-bit FP format operation 3610 performed by an instruction pipeline 3600, according to embodiments. The instruction pipeline 3600 can be configured to perform the mixed mode 8-bit FP format operation 3610. The instruction pipeline 3600 can be used to accelerate hardware instructions can include the instruction fetch and decode unit 1421, which can fetch and decode hardware instructions, and a controller unit 3620 (such as the scheduler controller 1422) that can schedule decoded instructions to one or more execution units within the compute blocks 1424A-1424N (collectively referred to as compute blocks 1424) and/or the matrix accelerator 1423. The instruction pipeline 3600 can also include a selection circuit 3630, such as a collection of multiplexors (muxes), to route input data to the compute blocks 1424 and/or the matrix accelerator 1423 in accordance with the mixed mode 8-bit FP format encoded in the hardware instruction of the mixed mode 8-bit FP format operation 3610.

In one embodiment, a hardware instruction can be scheduled to the compute blocks 1424 and/or offloaded to the matrix accelerator 1423 (e.g., for computation using systolic array circuit 3640). The one or more hardware instructions and associated data to perform the mixed mode 8-bit FP format operation 3610 can be stored in the memory 3650. Output of the hardware instruction can also be stored in the memory 3650. The memory 3650 can be any of the memory described herein, including system memory 1412, GPGPU memory 1418, or one or more cache memories 1427, 1430 as in FIG. 14.

In one embodiment, the compute blocks 1424 can execute one or more hardware instructions to perform the mixed mode 8-bit FP format operation 3610 using processing unit 3660. The processing unit 3660 can include a combination of programmable and fixed function hardware that is configurable to perform the mixed mode 8-bit FP format operations. In some implementations, processing unit 3660 may be vector processing unit (VPU). In some implementations, processing unit 3660 may be a floating point unit (FPU). The processing unit 3660 may include a conversion circuit 3662, round-to nearest (RNE) rounding circuit 3664, and a special processing circuit 3666.

In some embodiments, the hardware instructions to perform the mixed mode 8-bit FP format operation 3610 provide mixed mode operations on 8-bit FP (e.g., BFLOAT8) input operands. The instructions would accept at least one 8-bit FP format (e.g., BFLOAT8) input operand, while the other input operands can be of IEEE-754 float or half float data formats.

The conversion circuit 3662 can include programmable and fixed function hardware to perform the conversion process described above. The conversion circuit 3662 can internally upconvert the 8-bit FP format (e.g., BF8) operand to a higher precision format to match the format of the other input operands and the operation is performed at higher precision. The data conversion of conversion circuit 3662 renormalizes the 8-bit FP format inputs to match the dynamic range of the target precision, and extends the mantissa with zeros on the least significant bits (LSBs). Subnormal values on the BFLOAT8 inputs are preserved and normalized to target precision. The RNE rounding circuit 3664 can include programmable and fixed function hardware to perform the RNE rounding of the converted data. The special processing circuit 6166 can include programmable and fixed function hardware that addresses corner cases encountered when converting and/or rounding the data, such as underflow, overflow, or de-normals, for example.

In some implementations, the instruction for conversion of 8-bit FP format data as described herein may take the following form:

mac <f32> <f32> <f32> <bf8> mac <f16> <f16> <f16> <bf8> sub <f16> <f16> <bf8> add <f32> <f16> <bf8> mul <f16> <f16> <bf8>  dst src0 src1 src2

Some of the 8-bit FP format mixed mode examples are as discussed as detailed below:

Instructions with two source operands (mov, add, cmp, sel, mul, etc.): one of the sources is 8-bit FP format (e.g., BFLOAT8), while another is higher precision type. The destination can be either 8-bit FP format or higher precision type.

Instructions with three source operands (mac, etc): one or two of the sources can be 8-bit FP format (e.g., BFLOAT8), while the others are of higher precision type. The destination can be either 8-bit FP format or higher precision type.

FIG. 37 shows an example schematic representation of a hardware circuit 3700 to perform mixed mode MAC operation using at least one 8-bit FP format operand, in accordance with embodiments. In one implementation, the hardware circuit 3700 may be implemented in processing unit 3660 described with respect to FIG. 36.

As shown in the example of FIG. 37, the hardware circuit 3700 to perform a mixed mode MAC operation accepts F16 (src1) 3704 and BF8 (src2) 3706 input operands and accumulates with the accumulated sum src0 (F16) 3702. The final output (dst (FP16) 3750) is converted to F16 output. Conversion circuits 3710 a, 3710 b, 3710 c internally upconvert src1 3704 and src2 3706 inputs to FP32. The conversion circuits 36710 a-c may be the same as conversion circuit 3662 described with respect to FIG. 36. In embodiments, the conversion circuits 3710 a-c can preserve subnormal values on all inputs (e.g., DAZ=0).

The multiplier 3720 can multiply the FP32 inputs received from the conversion circuits 3710 b, 3710 c to produce an intermediate output. The intermediate output from the multiplier 3720 is normalized and accumulated with src0 input 3702 (which was converted to FP32 format by conversion circuit 3710 a) at adder 3730.

Finally, another conversion circuit 3740 (which may be the same as conversion circuit 3662 of FIG. 36) converts the FP32 sum to FP16 output 3750. In embodiments, the conversion circuit 3740 preserves subnormal values on all output (dst) data types (e.g., FTZ=0).

FIG. 38A illustrates a set of instructions 3800 executable by a processing unit, according to embodiments described herein. FIG. 38A illustrates fields of the instructions 3800 to perform mixed mode operations using 8-bit FP format operands. The instructions 3800 include, but are not limited to, a mixed mode mac instruction 3812, a mixed mode sub instruction 3814, a mixed mode add instruction 3816, and a mixed mode mul instruction 3818. Other mixed mode instructions for operation on 8-bit FP format operands may also be implemented by embodiments.

The instructions 3800 are executable by a processing unit, such as a VPU or FPU, provided by an embodiment. FIG. 38A illustrates fields of the instructions 3800, which, when executed, causes a processing unit to execute an instruction to perform mixed mode operations using 8-bit FP format operands. In one embodiment, the instructions 3800 includes an opcode field 3802 and operand fields to specify a destination 3804, zeroth source (src0) 3806, a first source (src1) 3808, and/or a second source (src2) 3810.

The opcode field 3802 can specify an opcode that identifies the instruction 3800 to execution logic. In one embodiment the opcode field 3802 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a processing unit of a compute block (e.g., compute block 1424).

The destination 3804, zeroth source 3806 (src0), first source 3808 (src1), and second source 3810 (src2) can be used to specify a destination to which a calculation is written and a location from which source data can be retrieved. In one embodiment the destination 3804 can specify a register to which data is to be written. In one embodiment the destination 3804 can be a scalar register, although in some embodiments the destination can also be a vector register that stores output from multiple channels. The zeroth source (src0) 3806, first source (src1) 3808, and second source (src2) 3810 can be registers or immediate values that include one or more channels of source data.

In some embodiments, additional fields other than those illustrated may be present. For example, in one embodiment a source modifier field is present which specifies the numeric modification of a source operand. The value of each data element of a source operand can optionally have its absolute value taken and/or its sign inverted prior to delivery to the execution pipeline. The absolute value modifier can be applied prior to the negate modifier, such that a guaranteed negative value can be produced. In one embodiment, a saturation field is present, which can be used to control destination saturation. When saturation is enabled, output data to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is an operation that converts any data that is outside the saturation target range for the data type to the closest represented value with the target range.

FIG. 38B illustrates a program code compilation process 3815, according to an embodiment. In one embodiment, a source code level description 3820 of a software program is compiled at a compiler 3830, which can include multiple levels of compilations, to a level having an operation 3840 that includes or specifies an 8-bit FP mixed mode instruction to be performed by processing logic. The operation 3840 can be an operation specified in an intermediate language or can be program code that references a primitive of a compute framework, such as a primitive provided by a machine learning framework. The operation 3840 that includes or specifies an 8-bit FP mixed mode instruction may then be further compiled by an additional compiler 3850, which can be a shader compiler, into machine level object code 3860 that includes an 8-bit FP mixed mode instruction to be performed by a processing unit (e.g., VPU, FPU) of a compute block, as described herein.

The following is an example of pseudo code to implement mixed mode 8-bit FP format operation, in accordance with embodiments.

F32 insrc0, insrc1, insrc2; if (OP is mixed_mode){ /* preserve subnormals on all inputs */  insrc0 = renormalize_extend_to_fp32 (src0);  insrc1 = renormalize_extend_to_fp32 (src1);  insrc2 = renormalize_extend_to_fp32 (src2); } else {  insrc0 = src0; insrc1= src1; insrc2 = src2; } F32 tmp1 = src1 * src2; F32 tmp2 = tmp1 + src0; F16 dst = convert_to_dst_format(tmp2); /* FTZ = 0 */ return dst;

FIG. 39 is a flow diagram illustrating an embodiment of a method 3900 for executing an instruction to perform mixed mode operations with 8-bit floating point format operands. Method 3900 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 3900 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-38 may not be repeated or discussed hereafter. In one implementation, a data processing system, such as data processing system 1400 of FIG. 14, may perform method 3900.

Method 3900 begins at processing block 3910 where a single instruction is fetched and decoded to be executed within a GPGPU. In one implementation, the single instruction decoded into a decoded instruction to cause the GPGPU to perform an 8-bit floating point format mixed mode operation. At processing block 3920, a set of commands is determined to execute the decoded vector instruction on a compute block of the GPGPU.

Subsequently, at processing block 3930, the set of commands is scheduled to a compute block of the GPGPU to execute the decoded instruction to perform the 8-bit floating point format mixed mode operation. Lastly, at processing block 3940, the decoded instruction is retired in response to completion of the set of commands.

FIG. 40 is a flow diagram illustrating an embodiment of a method 4000 for performing mixed mode operations with 8-bit floating point format operands. Method 4000 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions run on a processing device), or a combination thereof. The process of method 4000 is illustrated in linear sequences for brevity and clarity in presentation; however, it is contemplated that any number of them can be performed in parallel, asynchronously, or in different orders. Further, for brevity, clarity, and ease of understanding, many of the components and processes described with respect to FIGS. 1-39 may not be repeated or discussed hereafter. In one implementation, a processing unit, such as processing unit 3660 of FIG. 36, may perform method 4000.

Method 4000 begins at processing block 4010 where source values for an instruction are fetched for an operation to be executed by a computing block of a GPGPU. In one implementation, the source values are mixed mode 8-bit floating point format operands. At processing block 4020, source value inputs are re-biased and normalized as part of converting to a common binary format. Subsequently, at processing block 4030, the operation is performed on the source input elements in the common binary format.

Subsequently, at processing block 4040, operation outputs are normalized using shifters. Then, at processing block 4050, the normalized output is converted to a destination format to generate a resulting value. Lastly, at processing block 4060, the resulting value is returned to a destination operand.

The following examples pertain to further embodiments. Example 1 is an apparatus to provide support for 8-bit floating point format operands in a computing architecture. In one embodiment, Example 1 is an apparatus to provide systolic dot product accumulate on 8-bit floating point format input operands. The apparatus of Example 1 includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

In Example 2, the subject matter of Example 1 can optionally include wherein the shifters are to normalize output of the multipliers. In Example 3, the subject matter of any one of Examples 1-2 can optionally include wherein the multipliers comprise at least one of 4-bit multipliers, 8-bit multiplier, 16-bit, or 32-bit multipliers. In Example 4, the subject matter of any one of Examples 1-3 can optionally include wherein the adder comprises an adder tree that is to add products generated by the multipliers that are normalized by the shifters, and wherein the adder is to round a result of the adder tree using round to nearest even.

In Example 5, the subject matter of any one of Examples 1-4 can optionally include wherein the result is rounded to a destination precision indicated by the decoded instruction. In Example 6, the subject matter of any one of Examples 1-5 can optionally include wherein the systolic dot product circuitry to perform late accumulation of an accumulator source operand, the late accumulation to accumulate the accumulator source operand subsequent to generation of the dot product of the 8-bit floating point operands. In Example 7, the subject matter of any one of Examples 1-6 can optionally include wherein the systolic dot product circuitry to perform accumulation of an accumulator source operand, the accumulation to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuitry or at an intermediate stage of the systolic dot product circuitry.

In Example 8, the subject matter of any one of Examples 1-7 can optionally include wherein the processor comprises a graphics processing unit (GPU). In Example 9, the subject matter of any one of Examples 1-8 can optionally include wherein the apparatus is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.

Example 10 is a method for facilitating supporting 8-bit floating point format operands in a computing architecture, the method comprising: decoding, by a processor, an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; scheduling, by the processor, the decoded instruction and providing input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and executing, by systolic dot product circuitry of the processor, the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

In Example 11, the subject matter of Example 10 can optionally include wherein the shifters are to normalize output of the multipliers, wherein the adder comprises an adder tree that is to add products generated by the multipliers that are normalized by the shifters, and wherein the adder is to round a result of the adder tree using round to nearest even. In Example 12, the subject matter of any one of Examples 10-11 can optionally include wherein the result is rounded to a destination precision indicated by the decoded instruction. In Example 13, the subject matter of any one of Examples 10-12 can optionally include wherein the multipliers comprise at least one of 4-bit multipliers, 8-bit multipliers, 16-bit multipliers, or 32-bit multipliers.

In Example 14, the subject matter of any one of Examples 10-13 can optionally include further comprising performing, by the systolic dot product circuitry, late accumulation of an accumulator source operand, the late accumulation to accumulate the accumulator source operand subsequent to generation of the dot product of the 8-bit floating point operands. In Example 15, the subject matter of any one of Examples 10-14 can optionally include further comprising performing, by the systolic dot product circuitry, accumulation of an accumulator source operand, the accumulation to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuitry or at an intermediate stage of the systolic dot product circuitry.

Example 16 is a non-transitory computer-readable medium for facilitating supporting 8-bit floating point format operands in a computing architecture. In Example 16, the non-transitory computer-readable medium can have instructions stored thereon, which when executed by one or more processors, cause the processors to: decoding, by the one or more processors, an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the one or more processors to perform a parallel dot product operation; scheduling, by the one or more processors, the decoded instruction and providing input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and executing, by systolic dot product circuitry of the one or more processors, the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

In Example 17, the subject matter of Example 16 can optionally include wherein the shifters are to normalize output of the multipliers, wherein the adder comprises an adder tree that is to add products generated by the multipliers that are normalized by the shifters, and wherein the adder is to round a result of the adder tree using round to nearest even. In Example 18, the subject matter of any one of Examples 16-17 can optionally include wherein the result is rounded to a destination precision indicated by the decoded instruction.

In Example 19, the subject matter of any one of Examples 16-18 can optionally include wherein the instructions cause the one or more processors to: perform, by the systolic dot product circuitry, late accumulation of an accumulator source operand, the late accumulation to accumulate the accumulator source operand subsequent to generation of the dot product of the 8-bit floating point operands. In Example 20, the subject matter of any one of Examples 16-19 can optionally include wherein the instructions cause the one or more processors to: perform, by the systolic dot product circuitry, accumulation of an accumulator source operand, the accumulation to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuitry or at an intermediate stage of the systolic dot product circuitry.

Example 21 is a system for facilitating supporting 8-bit floating point format operands in a computing architecture. In Example 21, the system includes a memory and one or more processors of a plurality of GPUs. The one or more processors of Example 21 are communicably coupled to the memory and comprise: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the graphics processing unit to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

In Example 22, the subject matter of Example 21 can optionally include wherein the shifters are to normalize output of the multipliers. In Example 23, the subject matter of any one of Examples 21-22 can optionally include wherein the multipliers comprise at least one of 4-bit multipliers, 8-bit multiplier, 16-bit, or 32-bit multipliers. In Example 24, the subject matter of any one of Examples 21-23 can optionally include wherein the adder comprises an adder tree that is to add products generated by the multipliers that are normalized by the shifters, and wherein the adder is to round a result of the adder tree using round to nearest even.

In Example 25, the subject matter of any one of Examples 21-24 can optionally include wherein the result is rounded to a destination precision indicated by the decoded instruction. In Example 26, the subject matter of any one of Examples 21-25 can optionally include wherein the systolic dot product circuitry to perform late accumulation of an accumulator source operand, the late accumulation to accumulate the accumulator source operand subsequent to generation of the dot product of the 8-bit floating point operands. In Example 27, the subject matter of any one of Examples 21-26 can optionally include wherein the systolic dot product circuitry to perform accumulation of an accumulator source operand, the accumulation to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuitry or at an intermediate stage of the systolic dot product circuitry.

In Example 28, the subject matter of any one of Examples 21-27 can optionally include wherein the processor comprises a graphics processing unit (GPU). In Example 29, the subject matter of any one of Examples 21-28 can optionally include wherein the apparatus is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.

Example 30 is an apparatus for facilitating supporting 8-bit floating point format operands in a computing architecture comprising means for decoding an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause a processor to perform a parallel dot product operation; means for scheduling the decoded instruction and providing input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and means for executing the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands. In Example 31, the subject matter of Example 30 can optionally include the apparatus further configured to perform the method of any one of the Examples 11 to 15.

Example 32 is at least one machine readable medium comprising a plurality of instructions that in response to being executed on a computing device, cause the computing device to carry out a method according to any one of Examples 10-15. Example 33 is an apparatus for facilitating supporting 8-bit floating point format operands in a computing architecture, configured to perform the method of any one of Examples 10-15. Example 34 is an apparatus for facilitating supporting 8-bit floating point format operands in a computing architecture comprising means for performing the method of any one of claims 10 to 15. Specifics in the Examples may be used anywhere in one or more embodiments.

Example 35 is an apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture, and in particular to facilitate converting floating point data to or from 8-bit floating point format data. The apparatus of Example 35 includes a processor of a plurality of graphics processing units (GPUs), the processor to: fetch source values for an instruction to be executed by a compute block of the processor, wherein the source value is converted to a different data format and the source value is at least one of an 8-bit floating point format operand or is to be converted to the 8-bit floating point operand; convert the source value to a sign magnitude format of a destination by rescaling, normalizing, and converting the source value; applying a round to nearest even to the converted source value; and return the converted and rounded source value as a destination value.

Example 36 is an apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture, and in particular to facilitate efficient stochastic rounding on floating point format data values. The apparatus of Example 36 includes a processor of a plurality of graphics processing units (GPUs), the processor to: fetch a source value for an instruction to be executed by a compute block of the processor, wherein the source value is converted from a higher precision floating point to a lower precision floating point; convert the source value to a sign magnitude format of a destination and normalize the converted source value; add a random number to the converted and normalized source value, the random number having a size determined based on data format of source and destination operands, and wherein the random number is obtained from a PRNG; perform exponent adjustment of a resulting sum and truncate the resulting sum to the size of a destination operand mantissa format to generate a resulting destination value; and return the resulting destination value.

Example 37 is an apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture, and in particular to facilitate hybrid floating point systolic operations. The apparatus of Example 37 includes a processor of a plurality of graphics processing units (GPUs), the processor to: fetch source values and a calculation depth for an instruction to be executed by a matrix operation accelerator of the processor, wherein the source values include hybrid 8-bit floating point format operands; re-bias and normalize the source value as part of converting to a common binary format; generate a set of products based on an element-wise multiply of the re-biased and normalized source values in the common binary format; normalize multiplier outputs and an accumulator input using shifters for each multiplier and for the accumulator input; calculate a sum of the set of normalized multiplier outputs and round the sum to a nearest even; and round the calculated sum to a destination output precision using round to nearest even.

Example 38 is an apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture, and in particular to facilitate mixed mode operations with 8-bit floating point format operands. The apparatus of Example 38 includes a processor of a plurality of graphics processing units (GPUs), the processor to: fetch source values for an instruction for an operation to be executed by a computing block of the processor, wherein the source values include mixed mode 8-bit floating point format operands; re-bias and normalize source values as part of converting to a common binary format; perform the operation on the re-biased and normalized source values in the common binary format; normalize outputs using shifters; convert normalized output to destination format to generate a resulting value; and return resulting value to destination operand.

The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. Persons skilled in the art will understand that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the features set forth in the appended claims. 

What is claimed is:
 1. An apparatus comprising: a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.
 2. The apparatus of claim 1, wherein the shifters are to normalize output of the multipliers.
 3. The apparatus of claim 1, wherein the multipliers comprise at least one of 4-bit multipliers, 8-bit multiplier, 16-bit, or 32-bit multipliers.
 4. The apparatus of claim 2, wherein the adder comprises an adder tree that is to add products generated by the multipliers that are normalized by the shifters, and wherein the adder is to round a result of the adder tree using round to nearest even.
 5. The apparatus of claim 4, wherein the result is rounded to a destination precision indicated by the decoded instruction.
 6. The apparatus of claim 1, wherein the systolic dot product circuitry to perform late accumulation of an accumulator source operand, the late accumulation to accumulate the accumulator source operand subsequent to generation of the dot product of the 8-bit floating point operands.
 7. The apparatus of claim 1, wherein the systolic dot product circuitry to perform accumulation of an accumulator source operand, the accumulation to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuitry or at an intermediate stage of the systolic dot product circuitry.
 8. The apparatus of claim 1, wherein the processor comprises a graphics processing unit (GPU).
 9. The apparatus of claim 1, wherein the apparatus is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.
 10. A method comprising: decoding, by a processor, an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; scheduling, by the processor, the decoded instruction and providing input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and executing, by systolic dot product circuitry of the processor, the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.
 11. The method of claim 10, wherein the shifters are to normalize output of the multipliers, wherein the adder comprises an adder tree that is to add products generated by the multipliers that are normalized by the shifters, and wherein the adder is to round a result of the adder tree using round to nearest even.
 12. The method of claim 11, wherein the result is rounded to a destination precision indicated by the decoded instruction.
 13. The method of claim 10, wherein the multipliers comprise at least one of 4-bit multipliers, 8-bit multipliers, 16-bit multipliers, or 32-bit multipliers.
 14. The method of claim 10, further comprising performing, by the systolic dot product circuitry, late accumulation of an accumulator source operand, the late accumulation to accumulate the accumulator source operand subsequent to generation of the dot product of the 8-bit floating point operands.
 15. The method of claim 10, further comprising performing, by the systolic dot product circuitry, accumulation of an accumulator source operand, the accumulation to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuitry or at an intermediate stage of the systolic dot product circuitry.
 16. A non-transitory computer-readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to: decoding, by the one or more processors, an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the one or more processors to perform a parallel dot product operation; scheduling, by the one or more processors, the decoded instruction and providing input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and executing, by systolic dot product circuitry of the one or more processors, the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.
 17. The non-transitory computer-readable medium of claim 16, wherein the shifters are to normalize output of the multipliers, wherein the adder comprises an adder tree that is to add products generated by the multipliers that are normalized by the shifters, and wherein the adder is to round a result of the adder tree using round to nearest even.
 18. The non-transitory computer-readable medium of claim 17, wherein the result is rounded to a destination precision indicated by the decoded instruction.
 19. The non-transitory computer-readable medium of claim 16, wherein the instructions cause the one or more processors to: perform, by the systolic dot product circuitry, late accumulation of an accumulator source operand, the late accumulation to accumulate the accumulator source operand subsequent to generation of the dot product of the 8-bit floating point operands.
 20. The non-transitory computer-readable medium of claim 16, wherein the instructions cause the one or more processors to: perform, by the systolic dot product circuitry, accumulation of an accumulator source operand, the accumulation to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuitry or at an intermediate stage of the systolic dot product circuitry. 